Abstract: In general, in one aspect, the invention features a method for reducing the elapsed period between the time an interrupt acknowledge is issued by a CPU and the time when the corresponding interrupt vector is received at the CPU. When a device connected to a lower speed bus sends an interrupt request, an interrupt queue device, connected to the CPU by a higher speed bus, intercepts the interrupt request, temporarily stores the corresponding interrupt vector and then responds to an interrupt acknowledge from the CPU by delivering the temporarily stored interrupt vector on the higher speed bus. In addition, the interrupt queue can deliver the temporarily stored interrupt vector to the CPU on a separate serial line.

Abstract: A keyboard scancode signal is processed by the following steps. In response to the scancode signal, and before capture of the scancode signal by a first program that would otherwise interfere with use of the scancode signal by a second program, causing execution of the second program. After execution of the second program, interaction with the first program is permitted.

Abstract: A method for hot docking and hot undocking a portable computer and a docking station. The portable computer and docking station are physically coupled via a shared PCI bus and an expansion connector. Varying length pins in the expansion connector generate docking and undocking handshaking signals used by microcontrollers in the portable computer and docking station. The portable computer and docking station are functionally connected via low on-resistance switches located in the portable computer. Following a docking event, closure of the switches connects the portion of the shared PCI bus in the docking station with the PCI bus in the portable computer. When the switches are open, the PCI busses are functionally isolated. Both the portable computer and the docking station also include a local arbiter for arbitrating and granting bus control requests from devices coupled to the shared PCI bus.

Abstract: Access to a bus in a computer system having a CPU and bus devices capable of running cycles on a bus is controlled by an arbiter. The arbiter grants access to the bus according to an arbitration scheme that depends on whether a request for the bus is pending from the CPU, in which a first arbitration scheme arbitrates between the bus devices, and wherein a second arbitration scheme arbitrates between the CPU and at least one other bus device if the CPU request is present.

Abstract: A computer method for filling a selected region in a target image includes determining an attribute of a seed pixel within the selected region, forming a mask image of the region based on identifying pixels that have the attribute, and filling the selected region based on the mask image.

Abstract: A projection apparatus provides a projection engine that supplies polarized light to a dielectric filter (or diffraction grating). The dielectric filter provides an array of pixels that each pass selected colors of light and reflect other colors. Each pixel is subpixelated (for example, red, green, and blue subpixels) so that a single subpixel passes a selected color (for example, red) and reflects the other colors (for example, green and blue). A digital micromirror device has an array of mirrors that correspond in number to the number of subpixels of the dielectric filter. Each of the mirrors provide "on" and "off" positions for selectively transmitting a desired color of light from the mirror to an image screen. The image screen receives light reflected by selected of the mirrors of the array of micromirrors when the selected mirrors are in the "on" position. The micromirror device can be controlled with a computer, television, signal, video signal, or the like.

Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available.

Abstract: Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory.

Abstract: A multiprocessor system includes first and second processing units. Each of these processing units includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. Each processing unit is reset in response to a system reset signal but only selected portions of the processing units are reset in response to a partial-reset signal. The system can also include a number other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.

Abstract: A method and apparatus for selecting and indexing stored information for subsequent retrieval. The indexing system of the present invention indexes pages by storing a reference to a graphic segment of the displayed original page (instead of a copy of the graphic segment) as an index entry. Retrieval of the original page or image is accomplished by choosing from a listing of several categories of indexes, and then selecting an index entry displayed in the index gallery. The present invention provides a selection method using a lasso-tap gesture that allows the user to select a portion of the text for indexing (or other operations) without disrupting the natural handwriting action. Selection is accomplished using a closed (or nearly closed) curve followed by a recognized gesture within the closed curve. A local minimum established by the end points of the closed curve must fall within a specified range to identify the closed curve as a selection lasso.

Abstract: A programmable memory device including a register that stores a programmable mode select bit, a data input, a control input and decode circuitry that decodes the mode select bit to determine whether the memory device operates in either a check mode or a mask mode. The control input receives at least one control bit for each data byte received by the memory device during a write operation or cycle. The function of the control bit(s) depends upon the mode select bit. In a check mode of operation, each control bit functions as a parity/check bit for a corresponding data byte, where the memory device stores the check bit with its corresponding data byte during each write cycle. In the mask mode of operation, each control bit functions as a mask bit for a corresponding data byte, where the memory device selectively stores or masks the data byte depending upon the state of the corresponding mask bit.

Abstract: Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used.

Abstract: A computer system including a modular keyboard assembly allows input device modules to be inserted into the keyboard assembly. The modular keyboard assembly includes a plurality of recessed opening in which an input device module can be inserted. A connector on the input device module mates with a connector in the recessed opening, thereby providing electrical contact between the input device module and the keyboard assembly. Each input device module can be replaced by the user with a different input device module providing flexibility to the user as well as minimizing the amount of cabling that typically confronts the user. A controller in the keyboard assembly determines the types of input device modules coupled to the keyboard assembly.

Abstract: A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

Abstract: A computer system implements a standard modem without the use of a microcontroller. Instead, a digital signal processor is provided on an expansion card, but with direct links to the computer system itself. The code usually implemented in the microcontroller is instead implemented as a virtual modem controller to be called by the operating system of the computer itself. Further, this virtual modem controller includes a virtualized UART, that appears to the operating system software as a hardware UART, with entry points for calls to replace input/output instructions. In this way, standard device driver code written to execute input/output operations is easily converted to operate with the "virtualized" UART.

Abstract: A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare.

Abstract: An audio circuit for a computer includes a bidirectional modem connection, a microphone input, first and second audio output channels, and an audio synthesizing circuit arranged to produce first and second synthesized audio channels. In a first mode of operation the first synthesized audio channel is applied to the first audio output channel and the second synthesized audio channel is applied to the second audio output channel. In a second mode of operation the first and second synthesized audio channels are combined into a monotonic signal and applied to the second audio output channel, and audio signals from the bidirectional modem connection are applied to the first audio output channel.

Abstract: The keyboard portion of a computer has a small toggle switch structure positioned among its keys and reachable by a user while his hands are in the home row typing position. The switch structure is used to selectively switch the computer between typing and cursor control modes. When the computer is switched to its cursor control mode by depressing a stick-like activation portion of the switch structure, a small video camera mounted above the keyboard monitors an observation zone above the keyboard. A cursor control system in which the camera is incorporated detects the presence of the user's hand in a first predetermined configuration within the observation zone, tracks the hand's cursor control movement through the zone, and correspondingly moves the cursor on the computer's display screen. To carry out a cursor "pick" function in conjunction with the repositioned cursor, the user reshapes his hand to a second predetermined configuration.

Abstract: A removable battery pack for powering a pen-based or portable computer system in which the battery pack blocks its terminals when inserted into an unknown system. The known system includes a power supply microcontroller which passes battery charge data back and forth between a memory located in the battery pack and the power supply microcontroller. A battery microcontroller, located in the battery pack, eavesdrops drops on the communication between the power supply microcontroller and the memory, and when it validates a known signature of this communication, the battery microcontroller then enables the terminals of the battery pack. A trickle discharge current flows from the battery pack whenever the battery pack is out of the known system to allow the power supply microcontroller to power up in the case of a dead auxiliary battery.