Abstract: An apparatus is described for providing power management of a computer. The apparatus includes circuitry configured to assert a power down signal when a low power mode is to be entered and to de-assert the power down signal when the low power mode is to be exited. An audio amplifier has a power input and a mute input, and a switch is connected to the power input and configured to selectively supply power to the power input. A power down circuit is provided responsive to the power down signal and connected to the mute input and the switch such that when the power down signal is asserted, the power down circuit activates the mute input and subsequently closes the switch, and when the power down signal is de-asserted, the power down circuit open the switch and subsequently deactivates the mute input.

Abstract: Converter topologies in which two separate switching transistors and two capacitors are used on the input side. Preferably the two transistors are switched alternately, to alternately pull down different nodes in an inductor-capacitor chain. Two capacitors are interposed in series between an input inductor on the input and a transformer primary winding. Preferably the two transistors are connected with their parasitic diodes in opposite senses, so that one can source current from a first node to ground when off, and the other can sink current from a second node to ground when off.

Abstract: A computer system having a processor, a microcontroller, a flash ROM is provided with an address remapper for handling warm-boot events, and an arbiter for selectively assigning the ownership of the flash ROM to either the microprocessor or the microcontroller. The arbiter assigns the flash ROM initially to the microcontroller when power is initially provided to the system. After the flash ROM boots up and checks the integrity of the flash ROM and updates the content of the flash ROM with valid firmware if necessary, the microcontroller releases the flash ROM to the microprocessor to enable the computer system to proceed with the normal boot-up process. In this process, various system self tests are performed. Next, the microprocessor copies or shadows one or more portions of the flash ROM BIOS into a main memory array. After the shadow operation, the processor sets a remap bit to indicate that the ROM BIOS content has been copied into the main memory array.

Abstract: An internal AC adapter which incorporates a space efficient EMI filter is positioned within a main chassis portion of a portable personal computer having at least one energy-demanding component also positioned within the main chassis portion. The internal AC adapter, which converts alternating current received from an alternating current main to direct current for transmission to the energy-demanding components, includes a first connector for electrically connecting the internal AC adapter to the alternating current main, a bridge rectifier circuit having an AC input side electrically connected to the first connector and a DC output side and a space efficient electromagnetic interference filter having an input side electrically connected to the DC output side of the bridge rectifier circuit and an output side. The bridge rectifier circuit converts alternating current received from the first connector to direct current for transmission to the electromagnetic interference filter.

Abstract: Computer-implemented method and apparatus and associated for constructing a network configuration map comprised of at least two interconnected network entities selected from a series of network entities. A series of configuration scripts, each corresponding to one of the series of network entities include a first section comprised of a first portion containing an icon file for generating an icon representative of the corresponding one of the series of network entities, a second portion containing a set of connection rules for the corresponding one of the series of network entities and a second section containing a series of executable instructions for constructing a configuration file for the network entity.

Abstract: A serial bus communications method and circuitry for low speed serial bus functions. Over a two-wire communications channel, a unidirectional clock line and a bidirectional data line are used to transfer data. A protocol defines permissions, acknowledgments, terminations and retries handshaking between points. Circuitry is provided for reducing the latency of the serial bus when cooperating with the low speed functions. A resistive connection scheme is disclosed for converting high voltage signals into lower voltage signals.

Abstract: A driver bundle including a compressed, executable and self-extracting host driver prepended to an adapter card driver to form a single executable driver bundle. The driver bundle has a size less than the maximum allowable size for a command file, which is 64 Kbytes as defined by MS-DOS.RTM.. The combined size of the expanded host driver and the adapter card driver is greater than the maximum allowable size. When the driver bundle is executed, it commands a processor of a computer system to expand and execute the host driver. The computer system includes a network adapter card with an adapter processor for executing the adapter card driver. When executed, the host driver commands the processor to retrieve and download the adapter card driver to the network adapter card for execution by the adapter processor.

Abstract: A method for transferring data through a bus bridge. The bus bridge includes a number of data buffers for storing data, prefetching data and write posting data. A device communicating with the bus bridge may reserve a buffer by one of two reservation mechanism. The reservation mechanism provides the bus bridge with the address and byte count. The reservation may also be forwarded to any upstream bus bridges. The reserved buffers are prefetched for efficient use of bus access. Data is prefetched and flushed according to alternative algorithms if a buffer is not reserved.

Abstract: An LCD display unit is provided with enhanced brightness and a widened viewing cone angle and is removably connected to the base portion of a notebook computer via an LVDS connector. The notebook computer is used as a portion of a desktop computing system that further includes a docking station and a specially designed pivot arm type display support structure. To incorporate the notebook computer into the desktop system, the LCD display unit is removed from its associated base portion, and the removed LCD display unit is plugged into a complementary LVDS connector portion on the support structure which is connected via LVDS cabling to an appropriate interface portion linked to the inserted notebook computer base portion in the docking station.

Abstract: A monitor and a slide-in PC tray are operatively disposed in a common housing in an all-in-one type personal computer. User operable control buttons are mounted on the front side wall of the housing, and the PC tray forwardly slides into the housing, toward the rear ends of the control buttons, through an opening in the rear side wall of the housing. A circuit board is supported within the housing inwardly adjacent the front wall, with depressible switches mounted on the unit being in an aligned, facing relationship with the inner ends of the control buttons. As the PC tray is slid forwardly into the housing, cooperating alignment structures on the tray and the housing facilitate the automatic mating of a pair of facing electrical connectors on the tray and the rear side of the circuit board to thereby electrically couple the switches to the electronic apparatus on the PC tray. Each control button, when pressed, activates its facing circuit board switch and thus the related circuitry on the PC tray.

Abstract: A drive bay opening in the front bezel portion of a tower type computer CPU unit is provided with a swing-out plastic access door. The door is pivotable between a closed position and a full open stop position in which it is outwardly pivoted more than ninety degrees away from its closed position. A specially designed concealed, break-away hinge structure removably interconnects the access door and front bezel portion and includes a pair of hinge arms projecting outwardly from the door and molded integrally therewith. Outer end tabs in the hinge arms have apertures therein that rotatably receive domed hinge pins within recesses in the bezel. In the event that the access door is forcibly pivoted outwardly beyond its full open stop position the domed hinge pins act as cams that torsionally deflect the hinge tabs out of engagement therewith. As a result, the door simply pops off the bezel without damaging either the door, the hinge structure or the bezel.

Abstract: A graphics controller for use in a computer system includes a run slice line draw engine to generate a line as a plurality of slices. The run slice line draw engine calculates the length of the slices responsive to line definition parameters, such as the coordinates of the two line endpoints. Groups of like-sized slices can be determined to decrease the computations necessary to compute the size of each slice. The slices can be either drawn to the display through the frame buffer or used as endpoints for other lines to be generated. To increase the speed of operation, while parameters requiring a division are being calculated, the partial quotient is being used to generate partial slices. Clipped lines can be generated in part using normal Bresenham techniques for partial slices and using the run slice techniques for the full slices entirely within a window.

Abstract: A PC system uses two different kinds of terminals both of which having different architecture from a traditional PC. A first kind of terminal receives and transmits high resolution information based on a relatively low resolution transmission link. This requires that software and intelligence be distributed between the PC and the terminal itself. A second kind of terminal device receives and transmits low bandwidth information, communicating with the PC or another terminal device, within a confined wireless network, or across another confined wreless network via a wired network. The device can be used within nanocells of coverage, and can move between the covered cells.

Abstract: A primary server/standby server network configuration according to the invention includes a primary server executing network operating system software and a standby server monitoring for the proper operation of the primary server, where both the primary server and the standby server are connected to a storage system. If the primary server fails, the standby server instructs the storage system to switch its hardware connections to the standby server, allowing the standby server to boot the operating system. This instruction is done via in-band signaling. Further, multiple primary servers can be backed up by a single standby server.

Abstract: A system for aligning and securing a first connector to a second connector includes structure for holding the first connector and structure for receivedly engaging the second connector. The structure for holding the first connector is designed to be linearly moveable and the structure for receivedly engaging the second connector is fixedly positioned relatively to the structure for holding the first connector.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs).

Abstract: A computer system which includes a DMA controller on the local I/O unit which can be programmed by either the host processor or the local processor. Semaphore flags and lock bits are provided to allow determination of control of the local DMA controller and for passing information. Additionally, data alignment and padding circuitry is provided. The circuitry is informed of the logical data arrangement desired or utilized by the host processor or other devices and knows the data arrangement of the local processor. The circuitry properly obtains and realigns the data based on the transfer direction and data arrangement. The circuitry further properly zero pads the data when realignment is such that padding is necessary.

Abstract: A computer system determines the presence of a device attached to a system bus that responds to I/O or memory reads by driving the data lines of that bus to values normally present on an undriven bus. The data bus is first driven to a value other than its undriven value, such as to 00h. Then, circuitry measures the time it takes on an I/O or memory read for the data bus to return to its normally undriven value. If the response time is less than the time it takes for an undriven data bus to return to its undriven state, then an expansion board is driving the data bus to its normally undriven value. This indicates that the expansion board is responding to an I/O or memory read on the data bus, even though it is responding by driving that bus to its normally undriven value. Further, by determining the maximum response time of a device, system performance is then improved by tuning cycle time to correspond to that maximum response time.

Abstract: A series of hard disk drives are secured atop molded plastic support trays slidably and removably received in opposing guide channel member pairs snap-fitted into opposite side walls of a sheet metal cage structure externally used in conjunction with a file server or other computer device. Snap-fitted into rear end portions of the trays are small printed circuit boards that are insertable into hot plug sockets at the rear of the cage. Forwardly projecting guard plates on the rear end of the cage block manual access to the board/socket interface, and the surface mounted grounding leads on the board extend rearwardly beyond its signal leads to enhance grounding safety during disk drive installation and removal. At the front end of each tray is a vertical support plate upon which LED indicating lights are conveniently mounted for the associated disk drive.