Abstract: A network (10) includes several local networks (32, 34, 36). Each local network (32, 34, 36) includes a repeater (12, 16, 20) coupled to data devices (14, 18, 22). The combination of the repeater (12, 16, 20) and the data devices (14, 18, 22) form a collision domain for managing communications within the local network (32, 34, 36). Uplink modules (40, 44) manage communications between the local networks (32, 34, 36) by isolating collision domains and generating collision indications when messages cannot be transmitted. The uplink modules (40, 44) may also implement bridging, routing, or filtering capabilities that inhibit transmission of an intra-network message beyond its local network (32, 34, 36).

Abstract: A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode.

Abstract: An apparatus and method are disclosed for buffering graphics commands in a video graphics system, and for implementing graphics macro commands. The invention makes use of off-screen portions of video memory to create a dynamic command FIFO for commands, and to store command sequences for later or repeated use ("macros"). A command FIFO controller is provided, along with an on-chip bus FIFO and an on-chip command buffer (which is also a FIFO). Several multiplexers are also provided, so as to enable the command FIFO controller to create several different paths for commands coming into the graphics controller. Incoming commands may be routed to the command execution circuitry in several different ways: through the bus FIFO and command buffer to the command execution circuitry, directly to the command execution circuitry by bypassing the bus FIFO and command buffer, or from the bus FIFO into video memory to be stored in a dynamic command FIFO and later retrieved and sent into the command buffer.

Abstract: A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. Detection logic, controller memory, processor and a communication unit are compiled as a system configured upon a PCB. The PCB is configured to maintain certain vital functions even if power supplied from an expansion bus ceases. The PCB may employ a battery which maintains processor and controller memory activities and communication therebetween for a period of time sufficient to sustain video screen information stored within the controller memory. Thus, decoupling circuitry is present which prevents drain upon the battery if the communication unit is not being used. The decoupling unit separates power and signal conductors between portions of the printed circuit board.

Abstract: An audio power management system for a computer to eliminate noise signals associated with the power-down and power-up operations of the computer during power management operations. The audio power management system asserts a speaker mute signal before power is removed from the amplifier to reduce transient conditions. During power up, the speaker mute signal is applied to the amplifier for a period after power is applied to the amplifier. This control is done from a single digital output.

Abstract: A forced flow of cooling air through a computer housing is created during operation of a specially designed CD ROM drive operatively disposed in the housing. The drive has a bladed carrying structure which supports a compact disc and is rotationally driven with the supported disc. Driven rotation of the bladed carrying structure creates the forced flow of cooling air within the housing without requiring additional space for a separate cooling fan therein. In two illustrated embodiments of the bladed carrying structure the created cooling air flow is generally parallel to the rotational axis of the compact disc, and in a third embodiment of the bladed carrying structure the created cooling air flow is generally transverse to the rotational axis.

Abstract: Operating heat generated by a PCMCIA card inserted into the base housing portion of a computer, representatively a notebook computer, is dissipated by a heat sink system disposed within the base housing. In response to insertion of the card into its associated support structure within the base housing, a metal heat sink plate member is resiliently pressed into firm engagement with a side of the inserted card by a spring member interconnected between the plate member and the card support structure. Card operating heat is efficiently transferred to the metal plate member by conduction. To dissipate the heat received by the plate member, a heat removing fluid is flowed against the plate member and caused to receive heat therefrom. Heat received by the fluid is then transferred to ambient air external to the computer to substantially lower the operating temperature of the inserted PCMCIA card.

Abstract: A notebook computer is provided with first and second different types of pointing device modules, representatively a pointing stick module and a touchpad module, that may be releasably and interchangeably installed on its base housing portion. Each module, when installed on the base housing, is automatically coupled to cursor control circuitry within the computer. Representatively, a convenient snap-in attachment structure is used to releasably connect each module to the computer base housing, and a removable computer component underlies and assists in supporting the removably installed pointing device module.

Abstract: A notebook computer is provided with a collapsible keyboard structure having keys supported on scissored linkage arm assemblies. In response to closing of the computer lid, key return spring portions of the keyboard are shifted away from their normal underlying relationships with the keys, and the scissored linkage arm assemblies and keys are forcibly retracted to storage and transport orientations. When the lid is subsequently opened, the key return spring portions, and a specially designed key preload member, are shifted relative to the retracted keys through an elevation stroke. During an initial portion of the elevation stroke, the key return spring portions engage the retracted keys and move them to extended positions in which the spring portions underlie the extended keys.

Abstract: A cache memory system utilizing asynchronous/synchronous burst counter circuitry which lessens the need for expensive, high speed data SRAM to achieve zero wait-state operation. The burst counter circuitry takes advantage of the fact that a read address is present on the address bus approximately one-halfway through the initial bus cycle (T1) during a burst read. Unlike synchronous prior art burst counters, burst counter circuitry according to the invention is configured to forward the address to asynchronous address decoders as soon as it is present, rather than waiting for the next rising edge of the processor clock. For accesses to the first cache line, the timing budget therefore includes the first complete clock cycle of a burst read (T2) plus an extra half-clock cycle from T1. The extra time is utilized to retrieve data from the data SRAM core for provision to the processor data bus at the end of the bus cycle T2.

Abstract: In accordance with the invention, a computer system is provided with a processor, a flash ROM, a microcontroller and an arbiter for selectively assigning the ownership of the flash ROM to either the microprocessor or the microcontroller. The arbiter assigns the flash ROM initially to the microcontroller when it boots up. After checking the integrity of the flash ROM and updating the content of the flash ROM with valid software if necessary, the microcontroller releases the flash ROM to the microprocessor to enable the computer system to proceed with the normal boot-up process. In this process, various system self tests are performed. Next, the microprocessor shadows one or more portions of the flash ROM BIOS into a main memory array. After the processor successfully boots up, the processor releases the flash ROM back to the microcontroller by writing a command to a mailbox register in the arbiter which places the microcontroller in an idle mode and by restarting the clock generator of the microcontroller.

Abstract: The present invention relates to a system and method for shadowing data of a first register and a second register of a computer system that share a common address. When a bus agent runs a write operation to the register address, retry logic of a first bridge circuit retries the write operation and masks access by the bus agent to the bus. Retry bus master logic reruns the write operation, in response to which the second bridge circuit subtractively decodes the rerun write operation and transfers the data to the second register. The bus agent is then allowed to retry the initial write operation, in response to which the first bridge circuit positively decodes the retried write operation and transfers the data to the first register. Thus, coherency is preserved between the first and second registers.

Abstract: A notebook computer is provided with a collapsible keyboard in which a dome sheet with elastomeric key return dome members thereon is horizontally shiftable through elevation and retraction strokes to respectively shift the keys between elevated operating positions in which the domes underlie and support the keys, and retracted positions in which the domes are shifted away from their key-underlying positions. A springless linkage structure interconnects the dome sheet to a cylindrical hinge area portion of the computer's lid housing which rotates with the lid housing as it is opened and closed. The linkage structure functions to drive the dome sheet through its elevation stroke during an initial portion of the lid housing's pivotal opening movement, and to drive the dome sheet through its retraction stroke during a terminal portion of the lid housing's closing movement. Force is exerted on the dome sheet by the springless linkage structure only during forced pivotal movement of the lid housing.

Abstract: An apparatus for handling bus error signals is provided for a computer having a processor, an interrupt controller, a first PCI bus with first PERR# and SERR# signals, and a second PCI bus with second PERR# and SERR# signals. The apparatus has a buffer with an input connected to ground, an enable input connected to the second SERR# signal, and an output connected to the first SERR# signal. When the second SERR# signal is asserted, the first SERR# signal is also asserted via the buffer and is provided to one input of the interrupt controller. In an alternate embodiment, the buffer enable input is connected to the first SERR# signal and the buffer output connected to the second SERR# signal. The apparatus also receives the first and second PERR# signals and logically ORs the signals together to generate a combined PERR# signal.

Abstract: An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels.

Abstract: Heat generated by a processor within the base housing portion of a notebook computer is received, spread, and dissipated through an exterior wall of the housing by a heat transfer pad structure in which a spaced series of porous plastic tube members, each having a quantity of purified water therein, are individually and sealingly encapsulated in partially evacuated pocket areas formed between two facing sheets of a high temperature polyimide film material. A metal heat receiving block member is positioned between and contacts the processor and a portion of one side of the pad structure, with the opposite side of the pad structure contacting the exterior housing wall.

Abstract: An apparatus supports the sharing of a resource among computer applications. The computer system has a processor which adapted for executing a first application in a first mode of operation and a second application in a second mode of operation. The computer system also has a communication port adapted to receive the resource. The communication port is normally allocated to receive accesses from the second application. The computer system also has a virtual port for emulating the communication port. The virtual port diverts accesses from the first application directed at the communication port and buffers the accesses in the virtual port. An arbitrator is connected to the processor, the communication port, and the virtual port. The arbitrator claims the communication port from the second application and forwards accesses received by the virtual port to the communication port if the first application is accessing the resource and if the communication port is idle.

Abstract: A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal.

Abstract: A page wide piezoelectric ink jet print engine and a method of manufacturing the same. The page wide ink jet print engine includes lower and upper body parts, each formed from piezoelectric material and having a plurality of generally parallel, spaced projections. Lower side surfaces of the projections of the lower body part are conductively mounted to corresponding bottom side surfaces of the projections of the upper body part to define a plurality of generally parallel, axially extending ink-carrying channels from which ink may be ejected.

Abstract: A current switch is provided which selects and monitors charge and discharge states of a battery pack of a computer system. The current switch provides a current sense signal which is an indication of the current in the battery pack in order that a charge control circuit can monitor the charge state of the battery pack. The gain of the current sense signal is adjusted, depending on whether the battery pack is in a fast charging, trickle charging, or discharging state when the computer system is in a standby mode. Thus, the current switch provides a sufficient current sense signal for accurate current measurements while dissipating little power for the various battery pack charge states.