Abstract: A method and apparatus for transferring heat from a PCMCIA card involves the use of an external heat transfer device for transferring heat from the PCMCIA card located inside a computer to the environment surrounding the computer housing. Heat may be transferred from the interior of the PCMCIA card to temporary heat sinks inside the card. An external heat transfer device may be connectable for heat transfer to the exterior. The heat transfer device may be releasably pluggable onto and unpluggable from the PCMCIA card.

Abstract: An adaptive read ahead cache is provided with a real cache and a virtual cache. The real cache has a data buffer, an address buffer, and a status buffer. The virtual cache contains only an address buffer and a status buffer. Upon receiving an address associated with the consumer's request, the cache stores the address in the virtual cache address buffer if the address is not found in the real cache address buffer and the virtual cache address buffer. Further, the cache fills the real cache data buffer with data responsive to the address from said memory if the address is found only in the virtual cache address buffer. The invention thus loads data into the cache only when sequential accesses are occurring and minimizes the overhead of unnecessarily filling the real cache when the host is accessing data in a random access mode.

Abstract: A system for performing on-line reconfiguration of a disk array in which a source logical volume is reconfigured to a destination logical volume. Disk array configuration is invoked if a new physical drive is inserted, or a drive is removed. Reconfiguration can also be performed if the user desires to change the configuration of a particular logical volume, such as its stripe size. The disk array reconfiguration is run as a background task by firmware on a disk controller board. The reconfigure task first moves data from the source logical volume to a posting memory such as RAM memory. The reconfigure task operates one stripe at a time, with the stripe size being that of the destination logical volume. Once a stripe of data is moved into the posting memory, it is written back to corresponding locations in the destination logical volume. The reconfigure task continues until all data in the source logical volume have been moved into the destination logical volume.

Abstract: A computer system having a virtual drive array controller incorporated therein. The virtual drive array controller enables plural physical devices, which may be of a single type of device or a combination of multiple types of devices, to be represented to the computer system as a single logical drive. The virtual drive array controller includes a front end coupled to a secondary storage bus and a back end to which plural physical devices are coupled. Additional virtual drive array controllers may be arranged in a cascading configuration by coupling the additional virtual drive array controllers to the back end of the virtual drive array controller.

Abstract: A portable computer is provided with a rotary display screen cursor position control device that includes a rotatably supported disc member that has a radially extending depression formed in an exposed outer side surface thereof. To reposition the display screen cursor, the computer user places a finger in the depression and rotates the disc until the radially outer end of the depression points in a direction corresponding to the desired cursor repositioning movement direction, with the finger being placed at a radial position in the depression corresponding to the cursor repositioning velocity--a radially outer end portion of the depression corresponding to the highest selectable cursor velocity, and a radially inner end portion thereof corresponding to the lowest selectable cursor velocity.

Abstract: Electrical signals are received corresponding to sets of digital data, and output optical signals are delivered, corresponding to the digital data, on at least two optical channels corresponding to different sets of the digital data, using light from a single light source. In another scheme, the optical switch may be integrated with an optical transmission medium (e.g., an optical cable).

Abstract: A plurality of read-ahead FIFOs, each with an LRU replacement policy, is provided for enhancing buffer performance. The FIFO contains a plurality of adaptive buffer replacement counters to monitor usage statistics of the FIFOs and to identify one of the FIFOs as a refill candidate buffer in the event of a miss which requires new data to be brought into one of the FIFOs. Each FIFO has a hit detector and a flush detector for comparing the address of a data request from the bus master with the address stored by each buffer for indicating FIFO hit or invalidate operations. Each FIFO also has a buffer selector to provide data from the buffer selected by the hit detector to the bus master if the selected FIFO buffer has not been invalidated by the invalidate address comparator. The buffer selector otherwise transferring the requested data from the memory to the refill candidate buffer and presenting new data from the refill candidate buffer to the bus master.

Abstract: A method for use in upgrading a resource of a computer from an existing version of the resource to a later version of the resource. The method includes the steps of (a) digitally storing upgrade information which identifies the later version and describes features of the later version relative to one or more earlier versions of the resource, (b) digitally storing in the computer information identifying the existing version, by computer, automatically determining which of the earlier versions is the existing version, and (c) based on the results of the comparing step, automatically determining, or displaying to a user at least some of the upgrade information to aid the user in determining, whether to perform an upgrade. The upgrade information may be stored on a portable medium along with copies of the resources and the upgrade information may include instructions, in accordance with a predefined common syntax, for installing each of the resources.

Abstract: In a method and system of performing a write cycle to a memory address in a multi-processor system, a first write cycle is initiated to the memory address, and a second write cycle is initiated to the memory address. Data from the first and second write cycles is merged, and the merged data is written to the memory address.

Abstract: A method for configuring memory in a computer system. The method calls for determining the maximum configurable size of installed memory modules for each of a plurality of interleave options. The computer system is configured to utilize the largest of the maximum configurable sizes of interleave options. The maximum configurable sizes of interleave options are further compared to determine if the memory modules are installed in a manner providing the largest amount of configurable memory. If not, an error message is sent to the user.

Abstract: An improved printed circuit board layout is provided in which a transistor or a resistor (preferably a zero ohm resistor) can be installed. If a transistor is installed, this allows for selectively passing a signal; if a resistor is installed, the line is directly coupled. The resistor and transistor are surface mount devices, and the two pads for the resistor are overlapped with two of the pads for the source and the drain of the transistor. A separate pad is provided for the gate of the transistor. In this way, alternatively either a resistor or a transistor can be installed, but the trace links, stubs, and resulting undesirable effects are minimized through the overlapping pads.

Abstract: In accordance with the invention, a computer system is provided with a flash read-only-memory (ROM), a microcontroller and a data port. The microcontroller initially owns the flash ROM. The microcontroller further has a separate ROM upon which it can execute boot-up instructions. After booting up, the microcontroller checks the flash ROM contents, preferably by performing a check-sum of the flash ROM contents. If the checksum of the flash ROM contents matches an expected value, the microcontroller releases ownership of the flash ROM to the computer system so that the computer system boots-up as normal. If the microcontroller determines that the flash ROM has become corrupted, the microcontroller accesses the data port and looks for a flash programming protocol. If the protocol is present at the data port, the microcontroller receives the data from the data port and programs the flash ROM accordingly.

Abstract: An apparatus ensures that circuit cards of a computer system are properly oriented and fully inserted into their slots before allowing the computer system to power-up. Each card has two electrically connected key fingers on the card edge, while each slot has first and second contacts adapted to engage the two key fingers when the card is fully seated on the slot. One contact of the first slot is connected to a known voltage, while the second contact is connected to the first contact of the next slot. The second contact of the next slot is in turn connected to the first contact of the subsequent slot. Thus, upon a complete engagement of the cards onto the slots, all contacts are connected in a series arrangement. The final contact is connected to an insertion detector which turns on the computer system power supply only when the voltage of the last contact equals the known voltage, indicating that all circuit cards are fully seated on the slots.

Abstract: The present invention relates to a circuit that pulls down the power supply line in an electronic system to a low state when the electronic system is turned off. More specifically, the present invention is an active circuit that establishes a low impedance between a power supply line and a return line when a system's power is turned off, and establishes a high impedance between a power supply line and a return line when the system is turned on.

Abstract: A keyboard system according to the present invention includes a serial bus host controller coupled to a serial bus keyboard. The keyboard includes both keyboard scan logic and scan code conversion logic for passing to the host controller over the serial bus. The host controller includes circuitry for processing the data between the serial bus and a host bus. The host controller further includes 8042 emulation logic for providing a hardware compatible interface to the keyboard controller. The 8042 emulation logic also includes circuitry for communicating over the serial bus during times when the serial bus has not yet been initialized.

Abstract: A PCI repeater coupled between a primary bus and a secondary bus transparently decodes upstream transactions by halting operations on the secondary bus while the transaction is decoded on the primary bus. A clock disable signal is internally generated to temporarily disable the bus clock on the secondary bus. Transactions initiated on the secondary bus are first sent upstream regardless of whether or not the target is upstream. If the transaction is not positively claimed by a target on the upstream bus, the PCI repeater subtractively claims the transaction. Special upstream decoding logic in the PCI repeater is avoided by sending the transaction upstream and using the inherent decoding logic of PCI devices.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU.

Abstract: A method for controlling the power level of a computer system or the like provides a dual power range feature which allows a power supply to be used over a wide range of AC input voltages. The power control circuit employs a detector for the RMS voltage of the input power line, and a detector for the AC input current at the power line. These detected levels are applied to a multiplier to provide an indication of power input, multiplier output is compared with a reference to produce a control for the output power of the power supply. The duty cycle of an oscillator for an AC-to-DC conversion for a power factor control circuit within the power supply is the controlled element, using pulse width modulation. A dual power range is provided so that for low AC line voltages, where the AC line current would tend to be high, a lower power limit is in effect, then for higher AC line voltages, where AC line current is proportionally lower for a given power level, a higher power limit is allowed.

Abstract: An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.

Abstract: Circuitry for tristating the address and data outputs of a processor to prevent a deadlock condition when the processor and another bus master is accessing a shared resource. The processor is located on a local bus and the other bus master is located on a PCI bus. Bi-directional tristate buffers are placed between the address and data output pins of the processor and the address and data portions of the first bus. If the processor is requesting a local-bus-to-PCI-bus cycle, and the PCI bus master is asserting a request for a local bus shared resource, the processor address and data output pins are tristated by the tristate buffers to allow the PCI bus master cycle to proceed. After the PCI bus master cycle completes, the tristate buffers are reenabled to allow the processor cycle to complete.