Abstract: In one embodiment, control circuitry receives an indication of a current position of an input object on a capacitive touch sense device. The control circuitry determines whether a difference between a previous position and the current position exceeds a predetermined hysteresis threshold. If the determined difference does not exceed the predetermined hysteresis threshold, the control circuitry masks the current position of the input object on the capacitive touch sense device.

Abstract: Embodiments for constructing capacitance sensing devices include, but are not limited to, forming a plurality of electrodes on a central portion of a substrate, the substrate comprising a central portion and an outer portion, forming a first plurality of conductors on the substrate, each of the first plurality of conductors being connected to and extending from at least one of the plurality of electrodes, and forming an insulating material on the outer portion of the substrate and at least partially over some of the first plurality of conductors. The constructing also includes forming a second plurality of conductors on the insulating material, wherein the second plurality of conductors and the insulating material are configured such that each of the second plurality of conductors is electrically connected to at least some of the first plurality of conductors and is insulated from the others of the first plurality of conductors.

Abstract: A system and apparatus are described for providing greater flexibility and performance in a mixed-signal array through improved and highly configurable routing, control elements and signal processing capabilities.

Abstract: A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.

Abstract: A parallel pipelining method of operation of a touch sense controller for processing data into a touch map is disclosed. A current full scan of response signals to at least one excitation of a touch sense array is received using a first thread of a processing device. The current full scan of response signals is processed using a second thread of the processing device to render a touch map corresponding to the touch sense array. A next full scan of response signals is received using the first thread. Receiving the next full scan and processing the current full scan are performed substantially simultaneously.

Abstract: A spread spectrum slip time encoding scheme encodes data values with one or more Pseudo Noise (PN) codes and generates a corresponding PN encoded data stream. Other data values are encoded into the PN encoded data stream by varying a slip time between the 10 encoded data values.

Abstract: A circuit in accordance with one embodiment of the invention can include an LED drive circuit that may isolate a sense circuit from a supply voltage in a passive mode, and maintain a predetermined voltage difference between the sense circuit and the supply voltage in an operational mode.

Abstract: An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.

Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

Abstract: An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

Abstract: Embodiments of structures and methods for determining operating characteristics of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer are described.

Abstract: Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.

Abstract: An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

Abstract: A self-shielding capacitive sensor array may include a first plurality of sensor elements and a second plurality of sensor elements, where each of the second plurality of sensor elements intersects each of the first plurality of sensor elements, such that each of the first plurality of sensor elements may be capacitively coupled with each of the second plurality of sensor elements. The first plurality of sensor elements may be configured to shield each of the second plurality of sensor elements from a noise source.

Abstract: A method and apparatus for driving a stepper motor and using the stepper motor as a rotary sensor when the stepper motor is not being driven.

Abstract: An apparatus includes a data conditioning module configured to translate each of a plurality of signal strength values to a compensated signal value, where the compensated signal value is a function of its corresponding signal strength value.

Abstract: A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.

Abstract: An apparatus and method for selecting a keyboard key based on a position of a presence of a conductive object on a sensing device and a pre-defined area of the keyboard key. The apparatus may include a sensing device and a processing device. The sensing device may include a plurality of sensor elements to detect a presence of a conductive object on the sensing device. Multiple keyboard keys are assigned to pre-defined areas of the sensing device. The processing device is coupled to the sensing device using capacitance sensing pins, and may be operable to determine a position of the presence of the conductive object, and to select a keyboard key based on the position of the conductive object and the pre-defined areas of the sensing device.

Abstract: A method and a system for supplying power to a microcontroller with a single cell. One embodiment of the present invention discloses incorporation of a power supply pump circuit with the microcontroller and their dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.

Abstract: An improved method of framing data packets in a direct sequence spread spectrum (DSSS) system that uses one pseudo-noise code (PN-Code) to frame the packet with a start-of-packet (SOP) and end-of-packet (EOP) indicator, and a different PN-Code to encode the data payload. Furthermore, the SOP is represented by the framing PN-Code, and the EOP is represented by the inverse of the framing PN-Code. This method creates a robust framing system that enables a DSSS system to operate with a low threshold of detection, thus maximizing transmission range even in noisy environments. Additionally, the PN-Code used for the SOP and EOP indicators can be used to indicate an acknowledgement response.