Abstract: A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges.

Abstract: An intelligent power-on reset circuit in accordance with one embodiment of the invention can include a programmable voltage divider. The intelligent power-on reset circuit can also include a comparator that is coupled to the programmable voltage divider and that is coupled to receive a reference voltage. Furthermore, the intelligent power-on reset circuit can include a processing element that is coupled to the programmable voltage divider. The processing element can be coupled to receive programming for controlling a characteristic of the intelligent power-on reset circuit. The processing element can be for dynamically changing the programming during operation of the intelligent power-on reset circuit.

Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Abstract: An integrated circuit in accordance with one embodiment of the invention can include a plurality of storage elements that can be coupled in a first mode and a second mode. The first mode includes the plurality of storage elements being coupled to enable normal operation of the integrated circuit, and the second mode includes the plurality of storage elements being coupled together as a shift register. The integrated circuit also includes a rewritable non-volatile memory and a sleep controller that is coupled to the rewritable non-volatile memory. The sleep controller is for switching the plurality of storage elements between the first mode and the second mode. The sleep controller is for extracting data from the plurality of storage elements in the second mode and storing the data with the non-volatile memory to record the operating state of the plurality of storage elements in the first mode.

Abstract: An apparatus and method for selecting a keyboard key based on a position of a presence of a conductive object on a sensing device and a pre-defined area of the keyboard key. The apparatus may include a sensing device and a processing device. The sensing device may include a plurality of sensor elements to detect a presence of a conductive object on the sensing device. Multiple keyboard keys are assigned to pre-defined areas of the sensing device. The processing device is coupled to the sensing device using capacitance sensing pins, and may be operable to determine a position of the presence of the conductive object, and to select a keyboard key based on the position of the conductive object and the pre-defined areas of the sensing device.

Abstract: An interface circuit and method for programming or communicating with an integrated circuit (IC) via a power supply pin is provided herein. In general, the power supply pin may be coupled for receiving a relatively constant voltage signal during a first mode of operation (i.e., a normal mode) and a modulated voltage signal during a second mode of operation (i.e., a programming or communication mode). The interface circuit may be coupled between the power supply pin and other IC components for decoding the modulated voltage signal into data. Various encoding/decoding schemes may be used by the interface circuit and method for communicating data to the IC over the power supply lines. The decoded data may be used for programming or communication purposes.

Abstract: A clock generation circuit is provided for improving the accuracy of a low power oscillator circuit contained therein. The clock generation circuit includes a crystal-less oscillator having at least two distinct frequency modes, including a low frequency mode and a high frequency mode. In some cases, the crystal-less oscillator may be adapted to generate a first clock frequency with relatively high accuracy and a second clock frequency with relatively low accuracy. A calibration and control circuit is included within the clock generation circuit for increasing the accuracy of the second clock frequency. In particular, the calibration and control circuit increases accuracy by using the first clock frequency to calibrate the second clock frequency generated by the same crystal-less oscillator. A system comprising the clock generation circuit and methods for operating a crystal-less oscillator having at least two distinct frequency modes are also provided herein.

Abstract: A circuit includes first logic that generates a first signal suitable to activate at least one ESD clamp in response to an electrostatic discharge (ESD) event having a first severity or a second severity higher than the first severity, and second logic that generates a second signal suitable to activate the ESD clamp in response to the ESD event having the second severity, the second signal time multiplexed with the first signal.

Abstract: Disclosed is a peripheral device, comprising a sensor to trip when in proximity to a host device, and a transmitter coupled to the sensor to transmit a bind request to a host device. Further described is a method of binding the peripheral device to a host device.

Abstract: A method of defining a configuration of hardware resources, using a subgraph isomorphism process. The method executes a subgraph isomorphism process to discover possible resources in a hardware resource space that are suitable to implement a function. The hardware resource space may be defined by a target graph and the function may be defined by a subgraph. Next, the target graph is annotated to establish configuration settings for selected resources of the possible resources. The configuration settings may be established based on the subgraph mapping to the target graph. The target graph may also be annotated to specify parameters for the selected resources. This annotation may be performed in response to receiving parameters for the function.

Abstract: A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.

Abstract: An intelligent light source converts color and luminous flux data to luminous flux levels of individual color sources and automatically compensates for variations in operating conditions.

Abstract: Disclosed are a method and device for programming an array of memory cells.

Abstract: A method and system of automatically generating source code for configuring a programmable microcontroller. The method involves displaying virtual blocks in a computerized design system where the virtual blocks correspond to programmable circuit blocks in a microcontroller chip. The user selects a user module that defines a particular function to be performed on the microcontroller. The user assigns the virtual blocks to the user module. The design system then automatically generates source code for configuring the programmable blocks to perform the desired function. The source code can then be assembled, linked and loaded into the microcontroller's memory system. When executed on the microcontroller, the executable code will then set registers within the blocks to implement the function. Source code is automatically generated for: (1) realizing the user module in a hardware resource; and also (2) to configure the user module to behave in a prescribed manner.

Abstract: An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.

Abstract: A method and apparatus to implement a touch-sensor device using shared capacitive sensors. The apparatus includes a first plurality of sensor elements coupled together, a second plurality of sensor elements coupled together independently of the first plurality of sensor elements, and a third plurality of sensor elements coupled together independently of the first and second pluralities of sensor elements. The sensor elements of the first, second, and third pluralities of sensor elements are interspersed and disposed in a repetitive sequence along a movement path of a conductive object.

Abstract: A system includes an analog-to-digital modulator to convert at least one analog input signal into at least one digital output signal. The system also includes a processing device to set an operational order and a quantization level of the analog-to-digital modulator. The analog-to-digital modulator converts the analog input signal into the digital output signal according to the operational order and the quantization level.

Abstract: A technique for recognizing and rejecting false activation events related to a capacitance sense interface includes measuring a capacitance value of a capacitance sensor within the capacitance sense interface to generate a measured capacitance value. The measured capacitance value is analyzed to determine a baseline capacitance value for the capacitance sensor. The baseline capacitance value may be updated based at least in part upon a weighted moving average of the measured capacitance value. The measured capacitance value may also be analyzed to determine whether the capacitance sensor was activated during a startup phase and to adjust the baseline capacitance value in response to determining that the capacitance sensor was activated during the startup phase.

Abstract: An apparatus and a method for maintaining an output voltage of a charge pump circuit near a target voltage is disclosed. A regulated supply voltage is generated based on the output voltage of the charge pump. The regulated supply voltage is applied to a voltage input to the charge pump circuit and to a voltage input of a clock driver that provides a regulated clock signal to the charge pump circuit.

Abstract: Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a processor that translates different routing numbers received from the bus into different addresses and routing numbers for devices connected to the bridge. The bridge masks the fact that multiple MSC devices are coupled to it by reporting to the host that only a single device having multiple LUNs are coupled to the bridge.