Patents Assigned to Cypress Semiconductor
  • Light emitting driver circuit with compensation and method
    Patent number: 8093835
    Abstract: A light emitting driver circuit, system, and method are provided. The driver circuit system and method can be implemented in various ways. An embodiment includes a bypass circuit which diverts current from the LEDs whenever a switch coupled to the LEDs incurs residual current when turned off. In an additional or alternative embodiment, the residual current can be sensed and the amount of residual current used to trigger fetching of a compensation value. That compensation value can change a dimming function forwarded to the switch in order to compensate for, offset, or substantially eliminate the residual current through that switch.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: January 10, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kedar Godbole, Hariom Rai
  • Compensation circuit for a TX-RX capacitive sensor
    Patent number: 8093914
    Abstract: A capacitive sensor may include a transmit electrode and a receive electrode capacitively coupled with the transmit electrode. A capacitance sensing circuit senses a capacitance between the transmit and receive electrodes by applying a signal to the transmit electrode and rectifying a current waveform induced at the receive electrode. A compensation circuit reduces the effect of a mutual and parasitic capacitances of the transmit and receive electrode pair by adding a compensation current to the rectified current.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: January 10, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Andriy Maharyta, Viktor Kremin
  • Integration of non-volatile charge trap memory devices and logic CMOS devices
    Patent number: 8093128
    Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: January 10, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: William W. C. Koutny, Jr., Sam Geha, Igor Kouznetsov, Krishnaswamy Ramkumar, Fredrick B. Jenne, Sagy Levy, Ravindra Kapre, Jeremy Warren
  • Control circuit for optical transducers
    Patent number: 8093825
    Abstract: A method and apparatus for high-side control of an optical transducer provides improved current control and temperature compensation and uses stochastic modulation for improved spectral characteristics.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: January 10, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: David Van Ess, Patrick N. Prendergast
  • System for noise reduction in circuits
    Patent number: 8093765
    Abstract: Disclosed is an improved noise reducing apparatus using an anti-circuit, including a digital logic circuit and a digital anti-circuit corresponding to the digital logic circuit. The digital anti-circuit functions to cancel noise generated by the digital logic circuit. The anti-circuit includes logic to generate a similar number of switching edges as the logic circuit, where the anti-circuit edges are in the opposite direction as the logic circuit. The anti-circuit may have a circuit structure close to that of the noisy circuit, or can be formed of components different in structure but generating an output pattern similar to (and opposite from) the noisy circuit. In some embodiments, the differently structured components can include a state machine coupled to a memory or look-up-table.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: January 10, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: Paul Beard
  • Development, Programming, and Debugging Environment
    Publication number: 20120005693
    Abstract: A method includes receiving hardware description code that generically describes circuitry, and translating the hardware description code into one or more configuration files specific to a programmable system. The method further includes generating program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configuring the programmable system to implement the circuitry according to the configuration files and the program code.
    Type: Application
    Filed: January 10, 2011
    Publication date: January 5, 2012
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Haneef Mohammed, Jack Griffin, Christopher Keeser, Mark Hastings
  • Capacitive field sensor with sigma-delta modulator
    Patent number: 8089289
    Abstract: A capacitive sensor includes a switching capacitor circuit, a comparator, and a charge dissipation circuit. The switching capacitor circuit reciprocally couples a sensing capacitor in series with a modulation capacitor during a first switching phase and discharges the sensing capacitor during a second switching phase. The comparator is coupled to compare a voltage potential on the modulation capacitor to a reference and to generate a modulation signal in response. The charge dissipation circuit is coupled to the modulation capacitor to selectively discharge the modulation capacitor in response to the modulation signal.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: January 3, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Viktor Kremin, Andriy Ryshtun
  • Intelligent voltage regulator
    Patent number: 8089306
    Abstract: An intelligent voltage regulator circuit in accordance with one embodiment of the invention can include a variable voltage generator that is coupled to receive an input voltage. Additionally, the intelligent voltage regulator circuit can include a processing element that is coupled to the variable voltage generator. The processing element can be coupled to receive programming for controlling a characteristic of the intelligent voltage regulator circuit. The processing element can be for dynamically changing the characteristic during operation of the intelligent voltage regulator circuit.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: January 3, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: David G. Wright
  • Programmable digital-to-analog converter
    Patent number: 8089383
    Abstract: A multi-mode digital-to-analog converter (DAC) configured to operate in a plurality of modes.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: January 3, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Timothy J. Williams, James H. Shutt, Warren Snyder, Dennis Seguine
  • Programmable digital-to-analog converter
    Patent number: 8089384
    Abstract: A multi-mode digital-to-analog converter (DAC) configured to operate in a plurality of modes.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: January 3, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Timothy J. Williams, James H. Shutt, Warren Snyder, Dennis Seguine
  • On-chip power-measurement circuit using a low drop-out regulator
    Patent number: 8089822
    Abstract: A circuit and method are provided for controlling power consumption in an electronic circuit. Generally, the method involves measuring current flow through a memory core in the circuit, the memory core including a number of cells each with a number of active devices, and, if current flow exceeds a predetermined amount limiting it by applying reverse body bias to the active devices. In one embodiment, power is supplied to the memory through a low drop-out (LDO) regulator fabricated on a common substrate therewith, and the LDO regulator functions as a current mirror to mirror current through the memory core through a replica stack. Other embodiments are also disclosed.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: January 3, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Talluri V. Chankya, V. Sambasiva Rao
  • Charge accumulation capacitance sensor with linear transfer characteristic
    Patent number: 8089288
    Abstract: A method and apparatus for capacitance sensing uses an offset feedback voltage to linearize a charge-transfer characteristic.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: January 3, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: Andrey Maharita
  • Architectures for supporting communication and access between multiple host devices and one or more common functions
    Patent number: 8090894
    Abstract: A controller circuit can provide communication paths between multiple host devices and at least one function interface (I/F), where a function I/F can allow access to a predetermined circuit function. The controller circuit can include an endpoint buffer circuit having a plurality of storage locations configurable as endpoints according to a predetermined data transmission protocol and a data switching circuit coupled to the endpoint point buffer circuit. The data switching circuit is configurable to provide communication paths that enable a first host I/F and a second host I/F to access at least a same function I/F, and enable the first and second host I/Fs to communicate with one another.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: January 3, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hamid Khodabandehlou, Syed Babar Raza, Anup Nayak
  • Bidirectional slider with delete function
    Patent number: 8089472
    Abstract: A method and apparatus is disclosed herein for mapping a touch sensing device to two sets of output objects. In one embodiment, the method includes mapping a first set of output objects into a plurality of one dimensional positions of a touch sensing device when a presence of a conductive object is determined to be in a first region, among a plurality of regions, of the touch sensing device. The method further includes mapping a second set of output objects into the plurality of one dimensional positions of the touch sensing device when the presence of the conductive object is determined to be in a second region, distinct from the first region, of the touch sensing device.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: January 3, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jiang XiaoPing, Li GuangHai
  • Sequential deposition and anneal of a dielectic layer in a charge trapping memory device
    Patent number: 8088683
    Abstract: Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one embodiment, such a method is employed to form a dielectric layer having a stoichiometry attainable with only a deposition process but with a uniform material quality uncharacteristically high of a deposition process. In particular embodiments, sequential deposition-anneal operations provide an annealed first dielectric layer upon which a second dielectric layer may be left substantially non-annealed.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 3, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sagy Levy
  • Lattice Structure for Capacitance Sensing Electrodes
    Publication number: 20110316567
    Abstract: One embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element comprising a main trace, where the main trace intersects each of the first plurality of sensor elements to form a plurality of intersections. A unit cell may be associated with each of the intersections, and each unit cell may designate a set of locations nearest to the corresponding intersection. A contiguous section of the main trace may cross at least one of the plurality of unit cells. Within each unit cell, the second sensor element may comprise at least one primary subtrace branching away from the main trace.
    Type: Application
    Filed: August 5, 2011
    Publication date: December 29, 2011
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Min Chin Chai, Patrick Prendergast
  • ANTENNA WITH MULTIPLE FOLDS
    Publication number: 20110316756
    Abstract: An example antenna includes a first end portion, a second end portion, and an intermediate portion between the first end portion and the second end portion. The intermediate portion includes multiple folds. The second end portion includes a first conductor to couple with a communication interface of a communication module, and a second conductor to couple with a ground.
    Type: Application
    Filed: May 3, 2011
    Publication date: December 29, 2011
    Applicant: Cypress Semiconductor Corporation
    Inventors: Philip Pak-Lin Kwan, Paul Beard
  • Substrate bias feedback scheme to reduce chip leakage power
    Patent number: 8085085
    Abstract: A substrate bias circuit may measure a leakage current of a baseline device, compare the leakage current with a reference current, and based on the comparison, adjust a reverse body bias voltage applied to a body of the baseline device.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: December 27, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Vijay Kumar Srinivasa Raghavan, Iulian Gradinariu
  • Digital-compatible multi-state-sense input
    Patent number: 8085857
    Abstract: A method and an apparatus are described for sensing of a multi-state signal. An embodiment of a method includes driving a digital input line with a signal, the signal alternating between a first state and a second state. The method further includes sensing one or more values of the digital input line, and determining a state of the digital input line based on the sensed values.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: December 27, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventor: Jason Baumbach
  • Poly-phase frequency synthesis oscillator
    Patent number: 8085100
    Abstract: A frequency synthesis/multiplication circuit and method for multiplying the frequency of a reference signal. In one embodiment, multiple versions of the reference signal are generated having different phases relative to one another, and these multiple versions are combined to form an output signal having a frequency that is a multiple of the frequency of the reference signal.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: December 27, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventor: Aaron Brennan