Abstract: In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.

Abstract: A method and apparatus to recognize a tap gesture on a sensing device. The method may include detecting a presence of a conductive object on a sensing device, determining a velocity of the detected presence of the conductive object, and recognizing a tap gesture based on the velocity. The velocity may be determined by determining a differential of the capacitance over time on a sensing device. The sensing device may include a plurality of sensor elements to detect the presence of the conductive object, and a processing device may be used to determine the velocity of the presence of the conductive object, and to recognize a tap gesture based on the velocity of the presence of the conductive object.

Abstract: In one embodiment, a method for adding a new function type to an application development tool includes determining that a function specified by a user for a design of an application is of a new type, and presenting a user interface (UI) associated with the specified function. The method further includes creating custom metadata based on input provided by the user via the UI for the specified function, and converting the custom metadata into expression metadata having a format understandable by a code generator.

Abstract: Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element.

Abstract: A single cycle RISC CPU. The single cycle RISC CPU includes an instruction decoder configured to perform an instruction fetch and an instruction decode. An arithmetic logic unit is coupled to the instruction decoder. The arithmetic logic unit is configured to perform an instruction execute and produce a resulting data output. A register file is coupled to the arithmetic logic unit. The register file includes a register input and a register output. The register file is configured to provide data for the instruction fetch via the register output and accept the resulting data output via the register input such that the instruction fetch, the instruction decode, and the instruction execute are performed in a single clock cycle.

Abstract: A method in accordance with one embodiment of the invention can include transmitting wirelessly an encoded message that comprises reconciliation data to a host system. Additionally, an acknowledge packet can be received wirelessly from the host system, wherein the acknowledge packet corresponds to the encoded message. It can be determined if reconciliation data of the acknowledge packet has been changed in a predetermined way. If the reconciliation data of the acknowledge packet has been changed in the predetermined way, a peripheral device can be caused to enter a first mode.

Abstract: A system includes a controllable voltage generator to generate a power supply voltage. The system also includes a system controller to determine a voltage level associated with the power supply voltage, and prompt the controllable voltage generator to generate the power supply voltage. The system includes a floating gate reference device to generate an absolute voltage reference based, at least in part, on the voltage level associated with the power supply voltage. The system can also include analog circuitry to perform one or more electrical operations responsive to the absolute voltage reference from the floating gate reference device.

Abstract: A package and packaging method are provided that enable packaging of larger dies and/or smaller packages. Generally, the method includes steps of: (i) reducing a thickness of a portion of a top surface of leads of a leadframe extending into a package being formed; (ii) mounting a die to a paddle of the leadframe, the die extending past an edge of the paddle into a space created by reducing the thickness of the leads; and (iii) encapsulating the die and leadframe, including the reduced portion of the leads, in a molding compound. In one embodiment, the leads are reduced by half-etching the portion of the top surface. Preferably, the method further includes wire bonding pads on the die to etched portions of the leads to electrically couple the die to the leads. Alternatively, wire bonding is between the pads and non-etched portions of the leads. Other embodiments are also disclosed.

Abstract: An analog-to-digital converter (ADC) having a successive-approximation register digital-to-analog converter (SARDAC) is described.

Abstract: A device includes a first wireless transceiver adapted to communicate over a cellular network, a second wireless transceiver adapted to communicate over a local network separate from the cellular network, and a mechanism adapted to report movement information to a computer via the second wireless transceiver. The mechanism is optionally an optical sensor reporting relative position information. The device is operable as both a cellular communication device and a computer pointing device. A button of the device is adapted to operate as a mouse button, and optionally, in some modes, controls operation of the cellular communication device. The second wireless transceiver optionally uses Universal Serial Bus protocol. The device optionally transfers files via the second wireless transceiver. In some usage scenarios, the device and a separate wireless pointing device communicate with a same computer and are used to operate an application, such as a gaming application.

Abstract: A device for monitoring events. The device may have a programmable event engine for detecting events and a memory array coupled to the event engine. The array may store data for programming the event engine to monitor for the events. The device may have an external pin coupled to the event engine. The event engine may monitor a signal on the external pin to detect events external to the device. Alternatively, the device may output a signal on an external pin in response to detecting one of the events.

Abstract: A method of accessing a memory device multiple times in a same time period can include, in a first sequence of accesses, starting an access operation to one of a plurality of banks in synchronism with a first part of a first clock cycle and starting an access operation to another of the plurality of banks in synchronism with a second part of the first clock cycle, each bank having separate access circuits; and the time between consecutive accesses is faster than an access speed for back-to-back accesses to a same one of the banks; wherein during the access operations, storage locations of each bank are accessed in a same time period

Abstract: A method includes receiving an endpoint address and corresponding endpoint data, the endpoint address identifying a logical endpoint associated with the endpoint data, storing the endpoint data to at least one of a plurality of memory buffers corresponding to the identified logical endpoint, and transmitting the endpoint data to a destination according to the endpoint address. A peripheral device includes a logical-to-physical memory map to store an endpoint address and corresponding endpoint data received from a first device, the endpoint address to identify at least one data stream capable of transferring the endpoint data to a second device, and a service unit to retrieve the endpoint address and corresponding endpoint data from the logical-to-physical memory map, and to transfer the endpoint data to the second device in the data stream identified by the endpoint address.

Abstract: A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks.

Abstract: A high-frequency input circuit. The input circuit includes an input node, a bond pad, and a signal conversion resistor coupled in series between the input node and the bond pad to convert substantially all of a signal voltage at the input node to a signal current at the bond pad.

Abstract: A system comprises a temperature sensor generate multiple base-emitter voltage signals by sequentially providing various currents to a transistor, and a system controller to determine a differential voltage signal according to the multiple base-emitter voltage signals, the differential voltage signal proportional to an environmental temperature associated with the transistor.

Abstract: In one embodiment, an integrated circuit device includes an active area encompassed by a seal ring. The seal ring may include a deep moat formed on an outer edge of the seal ring. The deep moat may have a depth that extends substantially to the substrate to prevent cracks from propagating into the active area. Alternatively or in addition, the seal ring may include redundant vias.

Abstract: In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.

Abstract: A network interface to transport a continuous datastream over a frame-based transport network. The network interface includes a data input, an egress buffer circuit, a phase locked loop, and a data output. The data input receives frames carrying the continuous datastream from the frame-based transport network. The egress buffer circuit is coupled to buffer the continuous datastream and to generate a feedback signal based at least in part on a fill-level of the egress buffer. The phase locked loop is coupled to receive the feedback signal from the egress buffer and to recover a clock signal from the continuous datastream. The data output is coupled to output the data of the continuous datastream from the egress buffer circuit based on the clock signal.

Abstract: An embodiment of the present invention is directed to a method and system for electronic sensing of string instrument input. The method includes receiving a first signal from a peak detection circuit. The peak detection circuit is operable to sense string activation. A second signal is received from one or more capacitive sensors. The second signal may include finger placement information. The method further includes processing the first and the second signals to generate an audio signal and outputting the audio signal.