Abstract: An optical navigation system and method are provided. In one embodiment, the system includes: (i) a coherent light source to emit light to illuminate a portion of a finger; and (ii) a detector to receive light reflected from the portion of the finger, the detector including a speckle-based sensor configured to sense movement of the finger relative to the detector based on changes in a complex interference pattern created by the light reflected from the portion of the finger. Other embodiments are also described.
Abstract: In an embodiment, an apparatus includes a memory controller configured to control a plurality of daisy chained memory components connected over a daisy chained bus. The daisy chained bus includes a direct connection from the transmit interface of the memory controller to a receive interface of an initial memory component, and a daisy chain connection from a transmit interface of the initial memory component to a receive interface of a next memory component. A bus extends from a transmit interface of a last memory component directly to a receive interface of the memory controller.
Abstract: A self-calibration system includes a variable current source to generate a default source current for charging a capacitive load, and a load charge calibrator to detect a voltage associated with the capacitive load when charged by the default source current, and to generate a current control feedback according to the detected voltage and a desired charged voltage of the capacitive load, the current control feedback to indicate to the variable current source a charge current capable of charging the capacitive load to the desired charged voltage.
Type:
Grant
Filed:
June 26, 2007
Date of Patent:
October 11, 2011
Assignee:
Cypress Semiconductor Corporation
Inventors:
David Wright, Jason Muriby, Erhan Hancioglu
Abstract: A variable impedance sense (VIS) circuit (400) can detect a drift in the impedance of variable impedance circuits due to changes in operating conditions. Adjustments to binary impedance setting codes are made in response to a detected drift only when such changes do not increase a worst case variation from a target impedance. Adjustments can also be made in response to a detected input offset polarity.
Abstract: A method for queuing asynchronous memory accesses includes pinning memory buffers in a managed memory environment, issuing data transfer requests to a peripheral device, each request corresponding to at least one of the pinned memory buffers, and asynchronously accessing at least one of the pinned buffers responsive to the requests.
Abstract: An integrated circuit bridge device can include a first interface circuit coupled to a buffer circuit and a configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus. A second interface circuit can be coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit. In addition, a controller circuit formed in the same substrate as the first and second interface circuits can be configured to enable data transfers between the first interface circuit and the second interface circuits via the buffer circuit.
Abstract: A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.
Abstract: An amplitude control circuit (100) can include a peak level detect circuit (102) that generates a peak voltage signal (Vpeak?) based on a peak level of signal Xosc. An amplitude bias control circuit (104) can generate a bias voltage Vbc that can correspond to a peak amplitude of a received oscillator signal Xosc, and can change according to variations in a transistor threshold voltage due to process, operating conditions and voltage.
Abstract: The invention provides an improved remote control system utilizing a host device to configure a single remote control via a first communications link, wherein the remote control operates a plurality of devices via a second communications link.
Type:
Grant
Filed:
January 31, 2006
Date of Patent:
October 4, 2011
Assignee:
Cypress Semiconductor Corporation
Inventors:
John Wisniewski, Kristopher Young, David Wright
Abstract: A semiconductor structure has a substrate having a trench, an isolation dielectric in the trench, and a stress buffer layer, between the substrate and the dielectric. Semiconductor devices containing the semiconductor structure may have higher reliability, and may have a reduced manufacturing costs per device.
Abstract: Disclosed is a circuit for improved power management of a wireless device, comprising an input signal from an antenna, an oscillator, a mixer and a circuit for correlating. In a first analog embodiment of the circuit, the circuit for correlating comprises a surface acoustic wave (SAW) and the circuit further comprises an operational amplifier and a reference voltage. In a second digital embodiment of the circuit, the circuit for correlating comprises a digital correlator and the circuit further comprises a digital comparator.
Abstract: An optical navigation apparatus including a package incorporating a light source and a single die of silicon. The single die of silicon includes a photodiode array configured at the detection plane to receive the speckle pattern of the scattered light from the collection optics, circuitry configured to process signals from the photodiode array to determine changes in position of the apparatus relative to the tracking surface, analog circuitry configured to control and drive current through the light source, interface circuitry configured to communicate position data by outputting the position data via a data interface, a microcontroller comprising a processor core and memory for storing computer-readable code and data, and a system bus configured to communicate instructions and data between the microcontroller and said digital, analog, and interface circuitries. Other embodiments, aspects and features are also disclosed.
Type:
Grant
Filed:
January 22, 2008
Date of Patent:
October 4, 2011
Assignee:
Cypress Semiconductor Corporation
Inventors:
Steven Sanders, John Frame, Brian Todoroff, Yansun Xu
Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.
Type:
Application
Filed:
May 4, 2011
Publication date:
September 29, 2011
Applicant:
Cypress Semiconductor Corporation
Inventors:
David Wright, Jason Muriby, Erhan Hancioglu
Abstract: A wireless tracking device located in a vehicle, the device including a positioning system to periodically determine a location of the device, a processor connected to the positioning system to receive a vehicle sensor input indicating the vehicle status, a scanner to scan for an available wireless area network access point, and a wireless radio connected to the processor to transmit data to the available wireless area network access point.
Abstract: A voltage regulator and method of using the same are provided that improve wakeup-time and reduce power wastage in switching a device from standby or sleep-mode to active mode. Generally, the voltage regulator includes: (i) a standby regulator having a high-impedance node (NGATE); (ii) an active regulator having a high-impedance node (dominant pole node); (iii) a compensation capacitor; and (iv) a switching circuit to couple the compensation capacitor to the high-impedance node (NGATE) of the standby regulator while the device is in sleep-mode to pre-charge the compensation capacitor, and to couple the compensation capacitor to the high-impedance node (dominant pole node) of the active regulator while the device is in active or non-sleep-mode. Other embodiments are also disclosed.
Abstract: Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals. A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.
Type:
Grant
Filed:
December 27, 2007
Date of Patent:
September 27, 2011
Assignee:
Cypress Semiconductor Corporation
Inventors:
Bert Sullam, Warren Snyder, Haneef Mohammed
Abstract: A design tool provides interactive graphical pin assignment. In one embodiment, the design tool identifies layout restrictions of a configurable processing device that includes a plurality of pins. The design tool further provides an interactive visual representation of a pin assignment that accommodates the layout restrictions and a user input.
Abstract: One embodiment includes a system configured to identify a preferred channel for radio communication from a plurality of consecutive integer frequencies including preferred channels and non-preferred channels, the system further to generate a plurality of radio channels corresponding to a plurality of consecutive integer frequencies based on a generation of reference frequencies, identifies preferred channels and non-preferred channels from the plurality of radio channels, where frequency synthesizer settling times of the preferred channels are faster than frequency synthesizer settling times of the non-preferred channels, scan the preferred channels for radio activity, select one of preferred channels responsive to the scanned radio activity; and utilize one of the reference frequencies to generate a radio frequency corresponding to the selected one of the preferred channels.
Abstract: A method and packaging for semiconductor devices and integrated circuits is disclosed that eliminates warpage stress on packages caused by coefficient of thermal expansion (CTE) mismatch between the device, lead frame or die paddle and a molding compound. Generally, the method includes steps of: (i) mounting the die on which the device is fabricated to a die paddle of a leadframe; and (ii) encapsulating the die on the die paddle and at least a portion of the leadframe in a molding compound, wherein a difference between a first volume of molding compound above a plane of the leadframe and a second volume of molding compound below the plane of the leadframe is sufficiently reduced to substantially eliminate warpage of the finished package due to mismatch of CTEs of the device, lead frame and packaging compound. The die paddle may be etched or reduced to facilitate molding compound flowing under the plane of the leadframe. Other embodiments are also disclosed.