Abstract: A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with <100> crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.

Abstract: A method and apparatus for sensing a conductive object by a mutual capacitance sensing array is described according to an embodiment of the present invention. The mutual capacitance sensing array comprises one or more sensor elements. Each sensor element comprises an outer frame including a conductive material. A cavity is formed within the interior of the outer frame.

Abstract: A slider has a first conductive trace having at least one sub-trace and a second conductive trace having at least one sub-trace. The at least one sub-trace of the first conductive trace is interleaved with at least one sub-trace of the second conductive trace. Each sub-trace of the first and second conductive traces has a variable width from a first end to a second end of the slider.

Abstract: An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.

Abstract: A serial interface device may include a plurality of serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values.

Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dieletric thickness of less than approximately 20 angstroms.

Abstract: In one embodiment, a method for controlling display of data includes identifying a data item selected by a user from multiple data items displayed on a display screen, and modifying the appearance of the multiple data items. The method further includes causing the multiple data items to be displayed on the display screen in the modified form, together with additional information pertaining to the selected data item, where the additional information is presented without obscuring the multiple data items displayed on the display screen.

Abstract: Electromagnetic signals are sent between a base station and a human interface device (HID). Movements of the HID are detected according to an amount of time required for the electromagnetic signals to return back from the HID. In one embodiment, the electromagnetic signals are radio frequency (RF) waves carrying one or more pulses that are sent by multiple antennas in the base station and returned back from multiple antennas in the HID.

Abstract: A configurable power controller and method for controlling power of a macro circuit block, such as a memory circuit, in multiple power modes is described to help minimize power consumption of the macro circuit block when the application environment for the macro circuit block is in a lower power mode than during its normal power mode.

Abstract: An oscillator circuit and system are provided having a peak detector that can determine a peak voltage value from the oscillator. The peak voltage value can then be compared against a predetermined voltage value by a controller coupled to the peak detector. The comparison value is then used to change a bias signal if the peak voltage value is dissimilar from the predetermined voltage value. A variable capacitor or varactor can be formed from a transistor and is coupled to the oscillator for receiving the bias signal upon a varactor bias node. The bias signal is used to regulate the capacitance within the varactor as applied to the oscillator nodes. Another controller can also be coupled to the peak detector to produce a second bias signal if the peak voltage is dissimilar from a second predetermined voltage value. The second bias signal can then be forwarded into an amplifier having a variable gain to regulate the gain applied to the oscillator.

Abstract: Methods include performing a soft bulk programming operation in the memory array in a first cycle, performing a bulk erase operation in the memory array in a second cycle and, in a third cycle, selectively inhibiting one or more memory cells in the memory array while applying a programming voltage to the memory array.

Abstract: A circuit and method are provided for interrupting current flow into a voltage regulator from an output thereof when a voltage source (Vpwr) drops below an output voltage (Vout). In one embodiment, the circuit comprises: (i) a comparator supplied by Vout including an output and inputs coupled to Vpwr and Vout; and (ii) transistors coupled to and controlled by the comparator, including a first transistor configured to interrupt a first current path extending between Vout and Vpwr through an output-leg of the regulator when Vpwr drops below Vout. Preferably, the regulator includes a reference-leg and a feedback-circuit coupling Vout thereto, and the first transistor also interrupts a second current path between Vout and Vpwr through the feedback-circuit and reference leg. More preferably, the reference-leg comprises resistors through which it is coupled to ground, and the transistors include a second transistor to interrupt a third current path between Vout and ground.

Abstract: A programmable latch circuit (200) can include a volatile latch (206) that may regenerate a value determined by programmable section (202). In a test operation, a variable current source (216?) can generate a current (IBASE) that can be mirrored in test sections (252-0 and 252-1) and compared to a current drawn by either programmable element (210-0) or (210-1) by a latching operation of volatile latch (206). Variable current source (216?) can enable characterization of programmable elements (210-0 or 210-1) as well as adjustable test threshold limits. A program voltage (Vprog) applied to programmable elements (210-0 or 210-1) can be also be variable to allow for characterization of programmable elements (210-0 and 210-1) over a range of voltages.

Abstract: A differential sensing circuit and method for enhancing read margin of a memory device are disclosed. The differential sensing circuit includes a first current-to-voltage converter. The circuit includes a first current subtraction circuit having an erase reference cell. A first input terminal of the first current-to-voltage converter is coupled to the first current subtraction circuit. The circuit includes a second current-to-voltage converter. The circuit also includes a second current subtraction circuit having a program reference cell. A first input terminal of the second current-to-voltage converter is coupled to the second current subtraction circuit. Both the first and second current subtraction circuits are coupled to a memory access bias signal. Outputs of the first and second current-to-voltage converters are compared to generate an enhanced read margin output.

Abstract: Non-volatile (NV) semiconductor memories and methods of operating the same to reduce or eliminate a need for an external capacitance are provided. In one embodiment, the memory includes a memory cell comprising a random access memory (RAM) portion and a NV memory portion, and the method comprises steps of: (i) initially erasing the NV memory portion; and (ii) on detecting a drop in power supplied to the memory, programming the NV memory portion with data from the RAM portion while powering the memory from a capacitor. On restoration of power data is recalled from the NV memory portion into the RAM portion, and the NV memory portion erased. Preferably, the capacitor is integrally formed on a single substrate with the NV memory portion and RAM portion. More preferably, the capacitor comprises intrinsic capacitance between elements of the memory formed on the substrate. Other embodiments are also disclosed.

Abstract: One example of an ESD protection circuit (100) can include a p-channel field effect transistor (PFET) (110) having a source-drain path connected between a pad (102) and a protected circuit (106). In an ESD event, PFET (110) can provide an ESD discharge path between pad (102) and a high power supply node (114) or low power supply node (112).

Abstract: A charge pump circuit has at least three stages: a pre-stage, a common stage and post stage. Each stage has three devices which are common. An NMOS device, which is called the charge injection device (CID), is controlled by a PMOS device during charge injection and an NMOS device during charge trapping. Also, each of the stages includes comparison stages for the CID in order to minimize the bulk to source voltage (Vbs) or bulk to drain voltage (Vbd). This greatly improves efficiency during the charge injection phase. Furthermore, the post-stage includes a comparison stage for the PMOS device since the threshold voltage increases as you increase the number of stages with the bulk tied to VPWR. The PMOS comparison stage should be inserted at the stage where the PMOS device begins to operate in the sub-threshold region, which is technology and voltage dependent.

Abstract: A system and method comprising a non-volatile memory including one or more memory blocks to store data, a controller to allocate one or more of the memory blocks to store data, and a wear-leveling table populated with pointers to unallocated memory blocks in the non-volatile memory, the controller to identify one or more pointers in the wear-leveling table and to allocate the unallocated memory blocks associated with the identified pointers for the storage of data.

Abstract: A relatively precise and accurate current reference system and method are described. The present current reference system and method facilitate realization of relatively high accuracy and precision in current references independent of process, voltage and temperature (PVT) variations. In one embodiment, a current reference system includes an opamp (operational amplifier), a first transistor and second transistor, a first resistor and a second resistor of different temperature coefficients, and a third transistor and fourth transistor. The opamp indicates and corrects the potential difference between a first branch and a second branch. The first transistor and second transistor mirror currents in the first branch and the second branch. The first resistor and a second resistor of different temperature coefficients cause voltage drops across them in a manner that compensates for PTAT variations. The third transistor and fourth transistor provide voltages between respective bases and emitters.

Abstract: A wireless tracking device including a positioning system for determining a location of the device and a processor connected to the positioning system. The wireless tracking device further including a wireless radio connected to the processor for transmitting the location of the device across a wireless area network. A vehicle monitoring system including a sensor, a microcontroller configured to receive a sensor input from the sensor and determine a vehicle condition data, and a wireless transmitter in communication with the microcontroller. The wireless transmitter is configured to transmit the vehicle condition data to a remote data network access point. A method of monitoring a vehicle including determining a status of the vehicle, locating an available wireless data network access point, and transmitting the status of the vehicle though the access point.