Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Abstract: When wireless binding or pairing is required, two wireless devices change from a normal broad wireless operating range to a reduced wireless operating range. The wireless devices then conduct binding or pairing operations in the reduced wireless range. This prevents other wireless devices in the same area from detecting the same reduced range binding signaling and inadvertently binding with the wrong devices. After the reduced range binding operations are completed, the wireless devices automatically switch back to the broader normal wireless operating range and use the exchanged binding information for conducting normal wireless communications. The reduced range pairing scheme creates a simple and intuitive technique for pairing wireless devices without requiring the user to press buttons or select devices from a list.

Abstract: A system and method for matching the hardware resource requirements of a user module with the available resources of an underlying integrated circuit is shown. Databases are utilized to describe the requirements of a particular user module and the resources of a particular chip. A graphical interface is utilized to relate a selected user module with potentially appropriate resources, and to illustrate alternative placements. This graphical interface utilizes highlights of both the module and the associated resource in patterns, grayscales, or colors to graphically illustrate the relationship between the module and the associated resource.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a framer to receive packets, to determine a type associated with received packets, to pass data packets to a network processor, and to pass control packets to a host processor. The apparatus also includes a processor coupled to the framer to control the framer.

Abstract: Circuits including a laterally diffused output driver transistor and a distinct device configured to provide electrostatic discharge (ESD) protection for the laterally diffused output driver transistor are presented. In general, the device configured to provide ESD protection includes a drain extended metal oxide semiconductor transistor (DEMOS) transistor configured to breakdown at a lower voltage than a breakdown voltage of the laterally diffused output driver transistor. The laterally diffused output driver transistor may be a pull-down or a pull-up output driver transistor. The device also includes a silicon controlled rectifier (SCR) configured to inject charge within a semiconductor layer of the circuit upon breakdown of the DEMOS transistor. Moreover, the device includes a region configured to collect the charge injected from the SCR and further includes an ohmic contact region configured to at least partially affect the holding voltage of the SCR.

Abstract: A system, comprising: a plurality of modules, each module comprising a plurality of integrated circuits devices coupled to a module bus and a channel interface that communicates with a memory controller, at least a first module having a portion of its total module address space composed of first type memory cells having a first maximum access speed, and at least a second module having a portion of its total module address space composed of second type memory cells having a second maximum access speed slower than the first access speed.

Abstract: This invention provides a method for improved frequency agility and preferably includes transmitting and receiving data on a primary channel; finding a secondary channel substantially free from interference during a period between data transmissions on the primary channel; and transmitting and receiving data on the secondary channel when an unacceptable level of interference is detected on the primary channel. In an alternate embodiment, data is preferably transmitted on a primary and a secondary channel during separate periods of a transmission interval. If an unacceptable level of interference is detected on either the primary or secondary channels, then the other channel is used for data transmission during one of the periods while another one of the periods is used to identify a new channel substantially free from interference to replace the bad channel.

Abstract: A method includes receiving hardware description code that generically describes circuitry, and translating the hardware description code into one or more configuration files specific to a programmable system. The method further includes generating program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configuring the programmable system to implement the circuitry according to the configuration files and the program code.

Abstract: A circuit (200) can include a bias protection circuit (204) and a reference circuit (202). A bias protection circuit (204) can generate an internal power supply voltage (Vsuppi) from a higher device power supply (Vcch) with low voltage transistors and no resistors. A lower internal power supply voltage (Vsuppi) can be provided by buffer transistors (M5 and M6) that are biased according to limit section (206) that generates a bias voltage (biasn2) based on a threshold voltage drop and a feedback bias voltage (biasn1) from reference circuit (202).

Abstract: A programmable system includes a programmable analog system that is reconfigurable to perform various analog operations, and includes a programmable digital system that is reconfigurable to perform various digital operations. The programmable system also includes a microcontroller capable of reconfiguring and controlling the programmable analog system and the programmable digital system. The programmable digital system is configured to control the programmable analog system autonomously of the microcontroller.

Abstract: A method of measuring the temperature of device under test includes the steps of injecting a first current into an on-chip diode wherein a die containing the on-chip diode is under test. A second current is injected into the on-chip diode. A junction temperature is calculated based on the first current and the second current.

Abstract: An apparatus and method are disclosed synchronization of a clock signal to a data signal. The apparatus includes a phase lock and tracking logic circuit configured to detect a plurality of values. Each of the plurality of values indicates a position of a data edge of the data signal. The phase lock and tracking logic circuit adds the plurality of values to generate a result and to adjust the clock signal if the result is greater than a predetermined value, or threshold. The phase lock and tracking logic circuit may be configured to maintain the clock signal linearity approximately between the end of a first data packet and the beginning of a second data packet.

Abstract: A microcontroller with analog/digital Programmable System On-a-Chip (PSoC) architecture including multiple digital PSoC blocks and multiple analog PSoC blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The PSoC architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together.

Abstract: A processing device programming system automatically provides a user interface comprising a selectable list of one or more processing devices based on a system level solution, automatically generates an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices, and automatically programs the processing device according to the embedded programmable system solution.

Abstract: The invention has a bootstrapped high voltage pass gate transistor that couples the low voltage sense amplifier to the bitlines. Since the pass gate transistor is bootstrapped its gate floats to the high voltage of the power supply (VCC) plus a delta voltage. This overdrives the pass gate transistor and allows it to pass signals between the sense amplifier and the bitlines with low impedance. This results in good sense differential margins and fast read speeds. The circuit has a pass gate control circuit that places a negative high voltage signal on the gate of the pass gate during non-volatile write operations. This causes the pass gate to isolate the low voltage circuit from the high voltage circuits during this operation. Finally, the circuit is smaller than earlier column multiplexer circuits.

Abstract: An apparatus and a method to reduce temperature dependence of a reference voltage have been presented. In one embodiment, the method includes generating a reference voltage associated with a difference between a first threshold voltage of a first transistor and a second threshold voltage of a second transistor. The method may further include biasing the first transistor and the second transistor at a predetermined ratio of currents of the first and the second transistors to reduce temperature dependence of the reference voltage.

Abstract: A current sense amplifier can include an active load circuit having a first load device and second load device coupled in parallel to a first power supply node. A first load device and second load device can provide an impedance that varies according to a potential at a load control node. A reference current circuit can be coupled between the first load device and a second power supply node that includes a current reference section that provides an impedance according to a bias voltage. A data current circuit can be coupled between the second load device and a plurality of memory cells. An adaptive bias circuit can be coupled between the first power supply and the second power supply node and can include a bias section coupled to the load control node that provides an impedance according to the bias voltage.

Abstract: A circuit in accordance with one embodiment of the invention can include an LED drive circuit that may isolate a sense circuit from a supply voltage in a passive mode, and maintain a predetermined voltage difference between the sense circuit and the supply voltage in an operational mode.

Abstract: A test system has a package containing a number of die. There is a JTAG controller for each of the die. There is also master/slave selector input for each of the JTAG controllers. A boundary scan register link connects at least two of the die.

Abstract: A packaging structure and method are provided for packaging an optoelectronic device. Generally, the packaging structure includes: (i) an integrated circuit (IC) package to which the optoelectronic device is affixed; (ii) an optical plug mounted to the IC package, the optical plug positioned relative to the optoelectronic device to direct light to or from the optoelectronic device, the optical plug having an interior optical surface closest to the optoelectronic device that does not make physical contact with either the optoelectronic device or the IC package. Preferably, the packaging structure can further include air or an index matching fluid in a gap between the interior optical surface and the optoelectronic device or IC package. More preferably, both the IC package and the optical plug include features to facilitate alignment and mounting of the optical plug to the IC package during assembly. Other embodiments are also disclosed.