Abstract: A method and system for controlling the processing of an IC chip assembly line using a central computer system and a common communication protocol. In one embodiment, a manufacturing execution system (MES) is used as the computer system and the communications protocol is the standard semi equipment communications standard/generic equipment model (SECS/GEM). One or more equipment cell controllers (CC) may be used to communicate between the MES a plurality of in-line substations which comprise the assembly line. Automated vision camera systems may also communicate information to the MES via the CCs. In one embodiment, the MES maintains a database in memory comprising processing history of a die-strip and results of automated die-strip examination from the vision camera systems. In one embodiment, the die-strip may be of a ball grid array (BGA) type.

Abstract: Disclosed is a method of partitioning a memory, comprising dividing the memory into a first plurality of sub-zones, allocating a plurality of spare blocks in each of the first plurality of sub-zones, resizing the first plurality of sub-zones to a second plurality of sub-zones different from the first plurality, and reallocating the plurality of spare blocks among the second plurality of sub-zones. A circuit for an improved memory controller is described also.

Abstract: An apparatus and a method to initiate spread spectrum modulation have been presented. In one embodiment, a spread spectrum off to spread spectrum on transition circuit is used to start spread spectrum modulation. The spread spectrum off to spread spectrum on transition circuit may include a phase lock loop (PLL) to output a clock signal. The spread spectrum off to spread spectrum on transition circuit may further include a control block coupled to the PLL to cause the PLL to lock the clock signal to a predetermined center frequency before transitioning from a non-spread spectrum mode into a spread spectrum mode.

Abstract: A frequency synthesizer is described illustrating a system and method for modulation. In particular, the frequency synthesizer includes a control circuit for producing a plurality of input signals that is scalable to a frequency profile. Each of the input signals includes a slope and a direction of the slope. A higher order accumulator block is coupled to the control circuit and receives the plurality of input signals. The higher order accumulator block includes at least two accumulators. The higher order accumulator block sums the plurality of input signals to generate a standard curve that is non-linear. A frequency spreading control pattern generation modulator is coupled to the higher order accumulator block and modulates the standard curve to generate the desired frequency profile.

Abstract: A pulsed arbitration without coincidence detection system has a pulsed arbitration circuit that is controlled by an internal write pulse and a block/group row access and that has an output coupled to a sub-word line. A sub-word line area contains the pulsed arbitration circuit.

Abstract: System and methods to adjust a reference current are disclosed. A current reference circuit generates an adjustable reference current. A microprocessor-based feedback circuit adjusts the reference current, wherein the adjustment is based on read and write parameters attributed to a memory cell.

Abstract: A method and apparatus for reducing cross-talk between pixels in a semiconductor based image sensor. The apparatus includes neighboring pixels separated by a homojunction barrier to reduce cross-talk, or the diffusion of electrons from one pixel to another. The homojunction barrier being deep enough in relation to the other pixel structures to ensure that cross-pixel electron diffusion is minimized.

Abstract: Disclosed is a circuit comprising an inverter circuit which comprises inverters and level shifters; and a modulation circuit comprising a pull-up circuit and a pull-down circuit, the modulation circuit coupled to the inverter circuit to regulate the response of the circuit to an input voltage for various power supply voltage levels by the pull-up or pull-down circuit. Other embodiments are also disclosed.

Abstract: A method, apparatus or system for generating a clock signal that includes determining a transmission frequency within a first frequency range for receiving or transmitting a data stream, locking a clock to the transmission frequency during a packet exchange and tuning the clock to one or more frequencies within a second frequency range after the packet exchange. The clock may be variably tuned to multiple frequencies within either the first or second range.

Abstract: The apparatus includes a diode laser and a current source interconnected with the diode laser. Two independent circuits in the current source are configured to limit current flowing through the diode laser. A first current limiter circuit configured to limit a current output from the current source to an anode of the diode laser, and an independent second current limiter circuit configured to limit a current return from a cathode of the diode laser to the current source so that laser output power does not exceed a specified maximum regardless of a single fault in either the first or second current limiter circuits.

Abstract: A test circuit, system, and method are provided herein for testing one or more circuit components arranged upon a monolithic substrate. According to one embodiment, the system may include a test circuit and one or more circuit components, all of which are arranged upon the same monolithic substrate. In general, the test circuit may be configured for: (i) receiving an input signal at an input frequency, (ii) generating a test signal by modulating a phase of the input signal in accordance with a periodic signal, and (iii) supplying either the input signal or the test signal to the one or more integrated circuits, based on a control signal supplied to the test circuit. More specifically, the test circuit may be used to determine the jitter and/or duty cycle distortion (DCD) tolerance of any system component without changing the frequency of the clock signal supplied to the component or injecting noise into the clock recovery system.

Abstract: A method of communication between a first transceiver having a first local oscillator set at a first frequency and a second transceiver having a second local oscillator set at a second frequency disclosed. The method includes transmitting a first signal at a first frequency from the first transceiver to the second transceiver, transmitting a second signal at the second frequency from the second transceiver to the first transceiver, and receiving the second signal at the first transceiver. The method further includes maintaining the first local oscillator at the first frequency and the second local oscillator at the second frequency during the transmitting of the first signal, during the receiving of the first signal, during the transmitting of the second signal, and during the receiving of the second signal.

Abstract: A first capacitor and a second capacitor are charged until voltage at the second capacitor settles to a settling voltage. While charging, the first capacitor is alternately switched between a current source and ground. When the settling voltage is reached, charging of the first capacitor is halted. The second capacitor continues to be charged until voltage at the second capacitor reaches a reference voltage. The amount of time it takes for the settling voltage to reach the reference voltage corresponds to a measure of capacitance on the first capacitor.

Abstract: A blocking layer of a non-volatile charge trap memory device is formed by oxidizing a portion of a charge trapping layer of the memory device. In one embodiment, the blocking layer is grown by a radical oxidation process at temperature below 500° C. In accordance with one implementation, the radical oxidation process involves flowing hydrogen (H2) and oxygen (O2) gas mixture into a process chamber and exposing the substrate to a plasma. In a preferred embodiment, a high density plasma (HDP) chamber is employed to oxidize a portion of the charge trapping layer. In further embodiments, a portion of a silicon-rich silicon oxynitride charge trapping layer is consumptively oxidized to form the blocking layer and provide an increased memory window relative to oxidation of a nitrogen-rich silicon oxynitride layer.

Abstract: A synchronous memory with a shadow-cycle counter has a counter logic combiner with an address input, a registered processed-address input, an incremented-processed-address input, and a counter control input with an output that contains a processed address. A mask, counter, and mirror registers receives the processed address and has a clock input strobing around a middle of a pre-array clock cycle. An output of the mask, counter, and mirror registers forms a registered internal processed address. A clock phase shifter has a clock input and has an output coupled to the mask, counter, and mirror registers. A plane internal processed-address is coupled to the read/write control logic. An address output enable generated in the counter logic combiner is coupled to the data output enable logic.

Abstract: Disclosed is a circuit for encoding code phase modulated (CPM) signals, including a code storage device storing one or more PN codes, a counter, and a multiplexer coupled to the code storage device and the counter, the multiplexer to provide an encoded CPM sequence using the one or more reference codes.

Abstract: An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion.

Abstract: An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion.

Abstract: A method and apparatus to provide electrostatic discharge (ESD) protection to electronic circuits using a combination of low voltage and high voltage transistors.

Abstract: Wireless devices transmit and receive radio signals based upon reference frequencies that are generated by reference frequency circuits. If the reference frequency in the transmitter is different from the reference frequency in the receiver, the radio signals may not be received properly or may not be capable of being received at all. A measurement circuit measures the amount of error or signal corruption in radio signals due to the reference frequency offset. A trimming circuit then tunes the reference frequency in the transmitter or receiver to reduce the reference frequency offset.