Abstract: One embodiment relates to a laser positioning device for sensing relative movement between a data input device and a surface by determining displacement of image features in a succession of images of the surface. The device forms a single integrated package, which includes a planar substrate and a transparent encapsulant that also embodies a collimating lens. Both a coherent light source and a sensor array and associated circuitry are configured on the planar substrate. Another embodiment relates to a method of sensing relative movement between a data input device and a surface. Coherent light is emitted from a laser and collimated so as to form a collimated illumination beam with a predetermined diameter, D, and a substantially uniform phase front. A speckle pattern is generated by impingement of the collimated illumination beam on the surface and detected by a sensor array. Other embodiments are also disclosed.

Abstract: One embodiment relates to a method of sensing motion of an optical sensor relative to a surface. A first resolution and a second resolution are set. Measurement signals are obtained from a sensor array, and the motion of the optical sensor relative to the surface is tracked using the measurement signals. The tracking of the motion in a first dimension is performed at the first resolution, and the tracking of the motion in a second dimension is performed at the second resolution. Another embodiment relates to an optical sensor apparatus for sensing motion relative to a surface, wherein the tracking of the motion is performed at a variable resolution along each of two axes. Other embodiments and features are also disclosed.

Abstract: A fast lock circuit for phase lock loop comprising a frequency detector, a phase frequency detector, a logic unit and a corresponding charge pump for the frequency and the phase frequency detectors. Embodiments of the present invention use the logic unit to relay signals from the phase frequency detector circuit to the charge pump when the PLL is in lock. The logic circuit relay signals from the frequency detector circuit before the PLL is in lock. As a result, a constant current is supplied to a large loop filter capacitor before lock. In one embodiment, additional logic circuit may be used to maximize the output current. Therefore, using the logic circuit to supply constant current charges the large loop filter capacitor continuously and avoids a slow down in charging the large loop filter. Accordingly, current is no longer wasted and the lock time is improved.

Abstract: A method of full semiconductor chip timing closure includes the steps of determining a system level place and route. Next, a static timing analysis for each of a number of subsystems is performed. Finally, a full chip static timing analysis is performed.

Abstract: Disclosed is an improved noise reducing apparatus using an anti-circuit, including a digital logic circuit and a digital anti-circuit corresponding to the digital logic circuit. The digital anti-circuit functions to cancel noise generated by the digital logic circuit. The anti-circuit includes logic to generate a similar number of switching edges as the logic circuit, where the anti-circuit edges are in the opposite direction as the logic circuit. The anti-circuit may have a circuit structure close to that of the noisy circuit, or can be formed of components different in structure but generating an output pattern similar to (and opposite from) the noisy circuit. In some embodiments, the differently structured components can include a state machine coupled to a memory or look-up-table.

Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Abstract: A spread spectrum slip time encoding scheme encodes data values with one or more Pseudo Noise (PN) codes and generates a corresponding PN encoded data stream. Other data values are encoded into the PN encoded data stream by varying a slip time between the PN-encoded data values.

Abstract: A system and method are provided for screening a semiconductor laser. The method includes: (i) operating the laser at a first of a number of drive currents; (ii) acquiring a number (N) of frames of data from a sensor in an optical navigation system (ONS) receiving speckle pattern in light from the laser reflected from a surface proximal to the ONS, the sensor data including differential signal values; (iii) calculating an average differential signal value (AVG) for the N frames of data; (iv) sorting the N frames of data across a plurality of bins including a Bin_0 for frames of data having a differential signal value within a predetermined amount of the AVG; and (v) determining if a number of frames of data in any bins other than Bin_0 exceed a predetermined threshold, and if so recording the drive current.

Abstract: Disclosed is an apparatus for sensing a force, comprising an actuator having a conductive deformable surface, a substrate having a first conductive trace and a second conductive trace, a housing coupled to the actuator and to the substrate, holding the actuator in proximity to the substrate, and a circuit for measuring a capacitance value.

Abstract: An embodiment of the present invention is directed to a method and circuit to control light emitting diode (LED) output. The method includes receiving a line voltage signal which powers a lighting circuit comprising an LED and determining an adjustment of a threshold based on a variation of the line voltage signal and/or a controller delay or other practical controller limitation or imperfection. The method further includes dynamically adjusting a threshold or other reference of a controller which controls a switch of said lighting circuit for compensating for line variations to maintain a substantially uniform LED current.

Abstract: Embodiments of the invention relate to the testing and reduction of read disturb failures in a memory, e.g., an array of SRAM cells. A read disturb test mode may be added during wafer sort to identify any marginal memory cells that may fail read disturb, thus minimizing yield loss. The read disturb test mode may include first writing data to the memory. After a predetermined time period, the read disturb test mode reads data from the same memory, and compares the read data with the data previously written to the memory. A repair signal may be generated, when the read data is different from the data previously written to the memory. Additionally, a system may be implemented to reduce read disturb failures in the memory. The system may include a match logic circuit and a data selecting circuit. When a match condition is satisfied, data is read from a register that stores the previous written data, instead of from the memory. The match logic circuit may be selectively enabled or disabled.

Abstract: Phase-locked loop (PLL) fast lock circuit and method using a second frequency controlled feedback loop to complement a primary frequency and phase controlled feedback loop. The second loop may charge a capacitor controlling input voltage to a voltage controlled oscillator (VCO) up and down faster that the primary loop, such as using up and a down charge pumps. In some cases, the second loop uses a frequency detector to detect a difference between a reference and feedback signal frequencies; and in response uses logic to control two pump up and two pump down charge pumps. The frequency detector may be configured to receive a reset signal and a lock signal. The reset signal causes the second loop to send a strong pump up charge to the capacitor without waiting for a difference in the frequencies. The lock signal causes the frequency detector to stops counting the difference in the frequencies.

Abstract: A secure media device preferably includes a Universal Serial Bus (USB) Mass Storage Class (MSC) interface and a USB Human Interface Device (HID) interface. A storage media area is also preferably provided. The storage media is preferably divided into a secure and nonsecure area by arranging the storage media into multiple Logical Units (LUNs). The nonsecure area is preferably accessed in a conventional manner using a host USB MSC driver through the USB MSC interface on the storage device. A password dialog application can be located in the nonsecure area of the storage device.

Abstract: Optimizing a circuit by calculating at least one parameter of a circuit based on a first size of at least one sleep transistor, calculating at least one parameter of the logic circuit based on a second size of the at least one sleep transistor. This process may be repeated for different sizes of the at least one sleep transistor to determine an optimum size of the at least one sleep transistor to optimize at least one parameter of the logic circuit.

Abstract: A system and method for determining a SONOS VT window using a current sensing scheme is disclosed. The present invention creates a first current path and a second current path through the volatile and non-volatile sections of an nvSRAM memory cell. The erase threshold voltage of the first edge of the window is determined when current is detected in the first path. The program voltage of the second edge of the window is determined when current is detected in the second path. Accordingly, the voltage used to power a plurality of SONOS transistors may be set using the values of the first and second threshold edges to determine the VT window.

Abstract: A circuit and method for testing address uniqueness of a memory array are disclosed. The circuit includes a plurality of current sinks associated with rows and columns of the memory array. A plurality of word lines of the memory array are coupled to the plurality of current sinks. A current mirror circuit is coupled to the plurality of current sinks and a circuit output node is coupled to the current mirror circuit. The circuit output node is configured to compare a total current from tested word lines of the memory array with a predetermined reference current, and to output a test pass or test fail indication in response to the comparison.

Abstract: An apparatus and method for disabling an internal voltage regulator of a circuit to voltage stress test the circuit. The apparatus may include a circuit having an internal voltage regulator and a design-for-test circuit coupled to the circuit to disable the internal voltage regulator to voltage stress test the circuit in a test mode.

Abstract: A method and device for trading off inhibit disturb against bit-line disturb in a non-volatile memory where a threshold shift per inhibit disturb is increased, a threshold shift per bit-line disturb is decreased and the total threshold shift over the expected lifetime of the non-volatile memory due to inhibit disturbs is approximately equalized with the total threshold shift over the expected lifetime of the non-volatile memory due to bit-line disturbs.

Abstract: A method of mapping channels in wireless communications is discussed. The method determines error rates on potential channels to be used in a frequency hopping communication system. The error rates and then used in mapping data to the channels such that isochronous data is mapped to channels having lower error rates than others of the potential channels.

Abstract: Systems and methods of flyback capacitor level shifter feedback regulation for negative pumps. In accordance with a first embodiment of the present invention, a feedback regulator for a negative output charge pump comprises a flyback capacitor for inverting an output of the negative output charge pump to a positive voltage. The feedback regulator further comprises a voltage comparator for comparing the positive voltage to a reference voltage. The voltage comparator is also for producing an enable signal for control of pump driving signals to the negative output charge pump. The feedback regulator further comprises a first plurality of switches for selectively coupling a first terminal of the flyback capacitor between a low voltage and the output and a second plurality of switches for selectively coupling a second terminal of the flyback capacitor between a low voltage and the voltage comparator. Further, the feedback regulator comprises switch control logic for controlling the plurality of switches.