Abstract: A design tool, comprising a pattern injection tool configured to automatically allow for the inclusion of dummy structures, differential feature sizing and/or serif addition into integrated circuit (IC) designs, in a pre-processing stage.

Abstract: A programmable logic device comprising one or more memory circuits configured to check a cyclic redundancy check (CRC) value of an input and generate a CRC for an output.

Abstract: A method for processing a semiconductor topography is provided, which includes diffusing deuterium across one or more interfaces of a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In particular, the method may include diffusing deuterium across one or more interfaces of a SONOS structure during a reflow of a dielectric layer spaced above the SONOS structure. In some embodiments, the method may include forming a deutereated nitride layer above the SONOS structure prior to the reflow process. In addition or alternatively, the method may include forming a deutereated nitride layer within the SONOS structure prior to the reflow process. In some cases, the method may further include annealing the SONOS structure with a deutereated substance prior to forming the deutereated nitride layer. In either embodiment, a SONOS structure may be formed which includes deuterium arranged within an interface of a silicon layer and an oxide layer of the structure.

Abstract: An apparatus comprising a latch circuit, a non-volatile storage circuit, and a switching circuit. The latch circuit may be configured to be dynamically programmable. The non-volatile storage circuit may be configured to be re-programmable. The switching circuit may be configured to transfer data from (i) the non-volatile memory element into the latch circuit in response to a first control signal and (ii) the latch circuit into the non-volatile memory circuit in response to a second control signal.

Abstract: A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9.43 mA comprising the steps of (A) providing an address path configured to consume a maximum average operating current of approximately 2.38 mA, (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0.91 mA, (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0.94 mA and (D) providing a Q path configured to consume a maximum average operating current of approximately 0.61 mA.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises a first built in self test (BIST) circuit configured to test the first circuit. The second circuit generally comprises a second BIST circuit configured to test the second circuit. The second circuit may not be adjacent to the first circuit.

Abstract: An apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be configured to dominate if the first arbiter cell enters a metastable state. The selection device may be configured to provide arbitration between the first and second arbiter cells within a second predetermined time period.

Abstract: In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e.g., phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.

Abstract: A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. At least one of the plurality of signals may comprise an identical signal path while in the first mode and the second mode.

Abstract: A method for creating pinouts for inter-die connections comprising the steps of filling a number of columns of a computer readable file with information about pads and balls of the inter-die connections, marking portions of the computer readable file indicating a correlation between the pads and the balls, and generating a netlist according to one or more sets of computer executable instructions in the computer readable file.

Abstract: An apparatus comprising a first circuit. The first circuit may be configured to limit conduction between a first and a second power supply pin in response to one or more control signals. One or more of a plurality of paths may limit the conduction in response to one or more voltages.

Abstract: An apparatus comprising an output circuit and a control circuit. The output circuit may be configured to generate an output signal oscillating at a frequency in response to a control signal. The control circuit may be configured to generate the control signal in response to (i) a frequency of said input signal when in a first mode and (ii) a stored value when in a second mode.

Abstract: One aspect of the present invention concerns an apparatus comprising a circuit that may be configured to present a connection signal. The connection signal may be configured to automatically disconnect and reconnect a peripheral device from a host in response to one or more errors. In another aspect of the present invention the connection signal may be configured to shift a configuration of a peripheral device in response to one or more errors.

Abstract: A method of transferring of integrated circuit devices into and/or out of a plurality of underlying sockets having contacts and mounted to a board, comprising the steps of (A) disposing a socket presser block across at least some of the plurality of sockets, the presser block defining a matrix of cutouts and ribs and being configured to assume a first position in which the presser block is movable and a second position in which the matrix of cutouts is adapted to align with the sockets, (B) placing the presser block in the first position and moving the presser block so the cutouts are aligned with the sockets, and (C) placing the presser block in the second position and transferring the devices into and/or out of the sockets.

Abstract: A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow width effects.

Abstract: The present invention provides a method and architecture for allowing a device using a traditional one-time programmable technology to be programmed multiple times within the package. The present invention provides multiple programming without introducing the additional complexity of external pins or specialized packaging. An address counter and main array is provided using one-time programmable technology. The address counter selects a page in the main array to write the programmable information. The desired programming information is programmed into a first page while the additional pages remain unprogrammed. When additional information needs to be configured, the address counter is incremented and points to a new page in the main array where the new programming information may be stored. As a result, a number of programming configurations can be programmed into a one-time programmable technology.

Abstract: A circuit, method, and network are disclosed herein to implement a voltage-controlled LC oscillator. The oscillator is configured having an LC tank circuit which is modulated by an in-phase modulating voltage. The modulating voltage can have a phase angle and amplitude that is controlled. Depending on the values of those control signals, the oscillating voltage will either increase or decrease current within the LC tank circuit and, thereby, increase or decrease the oscillating voltage respectively. Any number of phases can be connected together to produce signals of dissimilar phase angles. Preferably, those signals have phase angles of 0°, 180°, or even fractions thereof if an external circuitry is applied to the oscillation network.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate (i) a first control signal, (ii) a second control signal, (iii) one or more first clock signals and (iv) a first data signal operating at a first speed in response to (i) an input data signal and (ii) a reference clock signal. The second circuit may be configured to generate one or more intermediate data signals operating at a second speed in response to (i) the first control signal, (ii) the one or more first clock signals and (iii) the first data signal. The third circuit may be configured to generate an output data signal operating at a third speed in response to (i) the second control signal and (ii) the one or more intermediate data signals.

Abstract: A method of validating data between a path generator and a path processor, comprising the steps of (A) transmitting validation data from said path generator to said path processor on a data path, (B) sequentially transmitting data on said data path, (C) determining if the transmitted data is valid in response to the validation data and (D) using the overhead data by the processor when the overhead data is validated by the validation data.

Abstract: A method and a structure are provided for measuring a concentration of an impurity within a layer arranged upon a semiconductor substrate. The method may include exposing the layer and semiconductor substrate to oxidizing conditions and determining a difference in total dielectric thickness above the substrate from before to after exposing the layer and substrate. The difference may be correlated to a concentration of the impurity. In some cases, the method may include designating a plurality of measurement locations on the layer such that a concentration profile of the impurity within the layer may be determined. In some embodiments, exposing the layer and substrate may include forming an oxidized interface between the layer and the semiconductor substrate. Preferably, the oxidized interface is thicker underneath portions of the layer with a lower concentration of the impurity than underneath portions of the layer with a higher concentration of the impurity.