Abstract: A deserializer within, for example, a transceiver is provided having multiple stages of pipelined demultiplexers. Each demultiplexer within the earlier stages of the pipelined architecture use only three latches. Two latches are dedicated to producing an odd bitstream (or even bitstream) from odd and even bits within the incoming serial bitstream. Another latch is dedicated to producing an even bitstream (or odd bitstream) from even and odd bits of the serial bitstream. Using only three latches within early stages of the pipelined architecture reduces power consumption and overall size of the deserializer. Clocking signal frequencies of subsequent stages are reduced and the clocking signals are delayed in order to align data outputs from the previous stage with transitions of clocking signals forwarded to the respective stages.

Abstract: A circuit comprising a first circuit and a second circuit. The first circuit may be configured to present information after a delay in response to a plurality of transmit and receive inputs. The second circuit may be configured to adjust the amount of delay prior to presenting information. The second circuit may be implemented as a state machine.

Abstract: A content addressable memory (CAM) (100) can include a number of CAM entries (102-0 to 102-n). Match indications from CAM entries (102-0 to 102-n) and mismatch indications from complementing circuits (106-0 and 106-n) can be supplied to a switching circuit (108). Mismatch indications can indicate if an entry mismatches data when compared with a comparand (104). In one mode of operation, a switching circuit (108) can provide match indications on a number of switch outputs (SW0 to SWn). In another mode of operation, switching circuit (108) can provide mismatch indications on a number of switch outputs (SW0 to SWn).

Abstract: A method for etching a dielectric layer formed upon a barrier layer with an etch chemistry including CxHyFz, in which x≧2, y≧2, and z≧2 is provided. Such an etch chemistry may be selective to the barrier layer. For example, the etch chemistry may have a dielectric layer:barrier layer selectivity of at least approximately 20:1, but may range from approximately 20:1 to approximately 50:1. Therefore, etching a dielectric layer with such an etch chemistry may terminate upon exposing an upper surface of the barrier layer. As such, a thickness of a barrier layer used to protect an underlying layer may be reduced to, for example, approximately 100 angstroms to approximately 150 angstroms. In addition, critical dimensions of contact openings formed with such an etch chemistry may be substantially uniform across a wafer. Furthermore, critical dimensions of contact openings formed with such an etch chemistry may be uniform from wafer to wafer.

Abstract: The invention provides a method and system for lookup (such as for example, lookup of message header information) that records information in a relatively large database in a relatively compact structure, while still providing for relatively rapid lookup and update. A relatively large but compact database includes a hybrid tree (or hybrid trie) structure, whereby information in denser portions of the database can be stored and retrieved from an identifiable leaf in the hybrid trie. The hybrid trie includes at least one leaf node marked to include a different data structure, whereby information in sparser portions of the database can be stored and retrieved from a more densely packed table.

Abstract: An improved wafer clamp retainer is provided. The retainer is used to movably secure a wafer clamp to an upper electrode within a parallel-plate reactor. When drawn downward, the wafer clamp is pressed by the retainer against an outer periphery of the wafer to hold the wafer against the lower electrode. When drawn upward, the retainer lifts the wafer clamp from the wafer so that the wafer can be accessed. The wafer clamp retainer includes one or more features formed about an outer surface of a shaft extending from one end of the retainer body. The feature can comprise one or more rings, or spiral threads which mate with a flexible washer. The washer can be pushed directly upon the shaft and snap-fitted with the features or, alternatively, threaded upon the shaft by employing mating features on the wall which surrounds the opening through the washer.

Abstract: An apparatus comprising an integrated circuit configured to operate in a plurality of signaling protocols. The integrated circuit may be configured to automatically select one of the plurality of signaling protocols in response to a signaling protocol of a connected bus.

Abstract: A circuit and method are disclosed herein for a multi-phase voltage-controlled LC oscillator. The oscillator is configured as a ring containing N sections, each of which has an LC tank circuit that determiines the oscillation frequency. All the oscillator sections produce a signal at the same frequency, but with a constant phase angle offset between one section and the next. Thus, for example, a 4-phase version of the oscillator would have 4 sections, producing signals with phase angles of 0°, 90°, 180°, and 270°. The phase offset in each section results from the use of amplified quadrature signals to drive the LC circuits. An advantage of this approach to obtaining multiple phases is enhanced frequency stability, since the LC circuits in the oscillator sections all operate at resonance. Frequency modulation is accomplished without the use of varactors or other voltage-controlled tuning devices.

Abstract: An apparatus including a clock generating circuit and a programmable logic circuit. The clock generating circuit may be configured to generate one or more output signals in response to a reference signal and one or more control signals, wherein the output signals each have a frequency and a phase that are dynamically variable. The programmable logic circuit may be configured to generate one or more of the control signals and receive the one or more output signals.

Abstract: A data transmission system (100) may include a transmitting portion (102) and a receiving portion (104). A transmitting portion (102) may include an encoder (106) that may encode data values of n bits into codes of m bits, where n is less than m. Codes may be transmitted with corresponding clock values. The absolute value of the DC component of a code summed with a corresponding clock value can be no more tan one for all code values.

Abstract: A method and computer aided system for predicting the reliability of oxide-nitride-oxide (ONO) based non-volatile memory. ONO memory devices may be programmed. Margin voltages may be recorded initially, and during baking at 100 degrees C. and 300 degrees C. From this data, constants and activation energy may be determined through a first formula. Frenkel-Poole activation energy may be determined. Through the use of a second formula, decay time of the information stored in the ONO memory may be predicted from the activation energy. The first formula may also be used to predict the decay time. The two decay time predictions may be compared to establish confidence. In this manner, data retention of an ONO memory may be reliably predicted.

Abstract: A programmable logic device comprising a macro-cell flip-flop configured to store (i) a first input when the programmable logic device is in a normal mode and (ii) a second input when the programmable logic device is in a test mode.

Abstract: An apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured to generate a first output signal having a first data rate in response to an input signal having a second data rate and clock signal having the second data rate. The second circuit may be configured to generate a second output signal in response to the input signal and the clock signal. The logic circuit may be configured to generate a clock signal in response to the first output signal and the second output signal.

Abstract: A method is provided, which includes patterning a stack of layers spaced below a sacrificial hardmask layer. In some embodiments, the method may include patterning a lower hardmask layer arranged above the stack of layers. Such a patterning process may include removing the entire sacrificial hardmask layer. For example, the method may include patterning an upper portion of the stack of layers using the sacrificial hardmask layer as a first mask and patterning a lower portion of the stack of layers using the lower hardmask layer as a second mask. Consequently, a semiconductor topography is provided herein which includes a sacrificial hardmask layer arranged above a plurality of layers. Such a sacrificial hardmask layer may include a material with substantially different etch characteristics than one or more upper layers of the plurality of layers and substantially similar etch characteristics as one or more lower layers of the plurality of layers.

Abstract: A ball grid array (BGA) package is disclosed. An interconnect structure is formed on a substrate that electrically connects the electrical device to be housed in the BGA package to the solder balls thereon. Contact pads are formed over the top surface of the substrate. These contact pads electrically connect to the interconnect structure. A layer of solder mask is formed over the substrate that includes openings that overlie the contact pads. The BGA is then completed using conventional process steps. Thereby, a BGA package is formed that includes contact pads disposed such that the contact pads are accessible from the top of the BGA package, making these contact pads easily accessible. Thus, when the BGA is attached to a circuit board, connection to circuits of the electrical device is obtainable.

Abstract: A clock may be combined with an asynchronous RAM to create an asynchronous RAM that works within a subset of a full clock period, but allows the address access and other internal RAM functions to occur throughout the clock period. The present invention simplifies the timing analysis of the logic path through the RAM, increases the clock frequency of the resulting logic (compared to a synchronous RAM with narrow timing window), reduces the current requirements (compared to asynchronous RAM), and allows the combinatorial logic to be changed late in the design cycle without the need for a RAM redesign. As more and more logic is synthesized and internal RAM is used to put increasing function on the same die, the structure of the present invention meshes well with synchronous synthesized logic design methodologies, while at the same time recognizes the need to be as stingy as possible with operating current.

Abstract: A semiconductor structure, comprises a semiconductor substrate, a gate layer on the semiconductor substrate, a metallic layer on the gate layer, and an etch-stop layer on the metallic layer. A distance between the substrate and a top of the etch-stop layer is a gate stack height, and the gate stack height is at most 2700 angstroms. In addition, the etch-stop layer has a thickness of at least 800 angstroms.

Abstract: An apparatus comprising a voltage controlled oscillator (VCO) within a phase lock loop (PLL) that may be configured to generate an output signal in response to (i) a low gain control input and (ii) a high gain control input. The low gain control input and the high gain control input are generally both active.

Abstract: A circuit, method and test architecture may be used for testing one or more integrated circuits that may be arranged upon a printed circuit board. Along with internal logic used by the integrated circuit during normal functioning, circuitry is included for built-in self-test. In an embodiment, the integrated circuits are semiconductor memories and include Memory Built-In Self-Test (MBIST) capability. A JTAG-compliant interface may be used to control the MBIST circuitry so that MBIST test modes can be selected by the JTAG Test Access Port controller, and MBIST test results can be written into boundary scan cells and scanned out through the JTAG Test Data Out port. The addition of a high-speed clock signal to the standard 4-wire JTAG interface allows full-speed operation of the MBIST circuitry. Therefore, the integrated circuit can be tested at full speed, and the test results scanned out by the slower JTAG clock.

Abstract: A method for determining device yield of a semiconductor device design, comprises determining statistics of at least one device parameter from at least two device layer patterns; and calculating device yield from the statistics. At least one of the device layer patterns is neither a diffusion layer pattern nor a gate poly layer pattern.