Patents Assigned to Cypress Semiconductor
  • Cascadable content addressable memory (CAM) device and architecture
    Patent number: 6763426
    Abstract: According to one embodiment, a CAM system (100) may include a plurality of CAM devices (102-0 to 102-n) arranged in cascade configuration. A CAM system (100) may include an input connection (104) that receives a request to perform a particular operation and an output connection (106) on which a CAM system (100) may provide a single response based on responses from each CAM device (102-0 to 102-n). In one particular approach, a request may flow through CAM devices (102-0 to 102-n) in a single direction from a first CAM device (102-0) to a last CAM device (102-n). Similarly, responses to requests may be generated in the same direction, from a first CAM device (102-0) to a last CAM device (102-n).
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: July 13, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: David V. James, Jagadeesan Rajamanickam
  • Array of dice for testing integrated circuits
    Patent number: 6759865
    Abstract: In one embodiment, a test interface for testing integrated circuits includes an array of dice. A removable electrical connection (e.g., an interposer) may be coupled between the array of dice and a wafer containing multiple dice to be tested. The removable electrical connection allows electrical signals to be transmitted between the array of dice and the wafer. The test interface may be used in conjunction with a tester.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: July 6, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Qi Gu, Bo Jin
  • Configurable and memory architecture independent memory built-in self test
    Patent number: 6760872
    Abstract: A circuit that may be used to support testing of a memory block. The circuit generally comprises a decoder and a generator. The decoder may be configured to (i) decode a command signal into an address field, an operation field, and a data field and (ii) present a control signal to the memory block in response to the operation field. The generator may be configured to (i) present an address signal to the memory block in response to the address field and (ii) present a data signal to the memory block in response to the data field.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: July 6, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Jay K. Gupta, Somnath Paul
  • Control transaction handling in a device controller
    Patent number: 6757776
    Abstract: Embodiments of the invention prevent data from being mishandled at a connected device using a system that verifies that data received after receiving a setup command portion of a control transaction is received without errors and/or without receiving a second setup command used to cancel the first. In some embodiments, a control transaction is processed by receiving a setup token and setup data, setting a predetermined memory location to write the setup data, and then preventing the setup data read from the memory from being acted on until the device verifies that no superceding commands have been received by the device.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: June 29, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventor: Frederick Pew
  • Architecture and logic to control a device without a JTAG port through a device with a JTAG port
    Patent number: 6757844
    Abstract: An apparatus comprising a first circuit comprising a JTAG port and a second port. A JTAG non-compliant circuit may be controlled by the JTAG port when connected to the second port.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: June 29, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Navaz Lulla, Anup Nayak, Harish Dangat, Richard L. Stanton
  • Low temperature metallization process
    Patent number: 6756302
    Abstract: The invention concerns a method of forming a layer of metal on a substrate and fill the via with high throughput. A layer of metal can be formed on a substrate using sequentially a cold deposition step, a slow hot deposition step and a rapid hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit a seed layer of metal over the entire surface on which the metal layer is to be formed. In the slow hot deposition step, further metal is deposited at a power allowing for surface diffusion of the deposited metal, which is then followed by a rapid hot deposition of metal under bulk diffusion conditions.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: June 29, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ende Shan, Gorley Lau, Sam Geha
  • Method of forming contact openings
    Patent number: 6756315
    Abstract: The present invention provides a method of forming, in semiconductor substrates, contact openings having low contact resistance. The method involves, in particular, the introduction of a “soft etch” cleaning step that is used to clean the bottom of the contact openings. The “soft etch” cleaning step uses fluorocarbon chemistry. It is shown that the resulting resistance of the contact openings is reduced.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: June 29, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hanna Bamnolker, Prashant Phatak, Usha Raghuram, Sam Geha
  • Technique for characterizing the performance of an object positioning apparatus
    Patent number: 6753944
    Abstract: In one embodiment, an object positioning apparatus is characterized by receiving sensor data from a sensor, processing the sensor data to compensate for sensor drift, and analyzing the resulting processed sensor data to determine a characteristic of the apparatus. Compensating for sensor drift cleans up the sensor data so that they may be properly analyzed and compared against known good sensor data, for example.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: June 22, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventor: Jonathan F. Dajnowicz
  • Apparatus and method for color data conversion
    Patent number: 6753988
    Abstract: A color data converter includes a plurality of memories configured to store lattice points for a color space. The lattice points of the first axis are assigned to memories in a sequential manner. The lattice points along the other two axes are assigned to memories in an alternating manner.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: June 22, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventor: James G. Eldredge
  • USB peripheral containing its own device driver
    Patent number: 6754725
    Abstract: A peripheral device comprising a computer readable media and an interface circuit. The computer readable media may be configured to store instructions for operating the peripheral device. The interface circuit may be configured to communicate the instructions to an operating system of a computer in response to connection of the peripheral device to the computer.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: June 22, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: David G. Wright, Frederick D. Jaccard
  • Programmable oscillator scheme
    Patent number: 6753739
    Abstract: A circuit including an oscillator circuit, a current generator circuit and a voltage generator circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The current generator may be configured to generate said first control signal in response to a first adjustment signal. The voltage generator circuit may be configured to generate the second control signal in response to a second adjustment signal.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: June 22, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Monte F. Mar, Warren A. Snyder
  • Semiconductor non-volatile memory device having an improved write speed
    Patent number: 6750102
    Abstract: A non-volatile memory IGFET device has a gate dielectric stack that is di lectrically equivalent to a layer of silicon dioxide having a thickness of to 170 Å or less. Above the dielectric stack is a polycrystalline silicon gate that is doped in an opposite manner to that of the source and drain regions of the transistor. By using a gate doping that is opposite to that of the IGFET source and drain regions the poly depletion layer that can occur during programming in modern and advanced memory devices is eliminated according to this invention. The device of this invention forms an accumulation layer in the poly rather than a depletion layer. This difference not only greatly improves the program speed, but allows for selecting the gate doping at levels as low as 1011/cm3, or less, without significantly compromising the program speed.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: June 15, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventor: Loren T. Lancaster
  • Token over ethernet protocol
    Patent number: 6751213
    Abstract: A token over Ethernet protocol is described which allows a plurality of ports connected to a shared channel to communicate with each other. The communication is controlled by tokens that are transmitted before the transmission of packets. A packet can contain digital data from a digital device such as a computer, or digitized voice signals from a voice device such as a telephone. Voice packets are given priority over data packets to minimize delays that might provide distortion to the received voice signal. Each transmitted token identifies the next port to transmit which is determined from a valid list maintained within each port. All ports can receive tokens and packets during any receiving cycle, but only the port authorized by the last transmitted token can transmit a token, or a token and a packet. All ports check each transmitted token for a turn at transmitting information.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: June 15, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Peter C. P. Sun, Gary J. L. Lin
  • Content addressable memory having redundancy capabilities
    Patent number: 6751755
    Abstract: According to one embodiment, a content addressable memory (CAM) (100) can include a number of ordinary rows (102-0 to 102-n) that provide ordinary match indications (Match0 to Matchn) as well as redundant rows (108-0 and 108-1) that can provide redundant match indications (RMatch0 and RMatch1). If an ordinary row (102-0 to 102-n) is defective, a redundancy multiplexer (114-0 to 114-n) can be switched to provide a redundant match indication (RMatch0 and RMatch1) as an input to a priority encoder (118) instead of the ordinary match indication from the defective ordinary row.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: June 15, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Stefan P. Sywyk, Eric H. Voelkel
  • Interface scheme for connecting a fixed circuitry block to a programmable logic core
    Patent number: 6747479
    Abstract: An apparatus comprising one or more configurable interface tiles. The configurable interface tiles may be configured to communicate one or more signals between one or more programmable logic cores and one or more fixed function cores. The one or more configurable interface tiles, the one or more programmable logic cores and the one or more fixed function cores may be integrated on a single chip.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: June 8, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Alan J. Coppola, Joel Stanley, Steven J. E. Wilton
  • PLD configuration port architecture and logic
    Patent number: 6748456
    Abstract: A programmable logic device (PLD) comprising a configuration controller. The configuration controller may be configured to (i) retrieve data and (ii) program a number of configuration bits of the PLD in response to the data.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: June 8, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Richard L. Stanton, Anup Nayak, Navaz Lulla, Harish Dangat
  • Method and apparatus for configuring an interface controller wherein ping pong FIFO segments stores isochronous data and a single circular FIFO stores non-isochronous data
    Patent number: 6745264
    Abstract: Hardware Description Language (HDL) code is created for an interface controller so that logic requiring device-specific configuration refers to a parameter file. This set of parameters lets components in a bridge circuit provide support for the same configuration. In another aspect of the invention, a control circuit identifies isochronous endpoints and non-isochronous endpoints. A buffer is configured into a first FIFO mode for isochronous endpoints and configured into a second FIFO mode for non-isochronous endpoints.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: June 1, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: David Luke, Frederick Pew, Kris Provencio
  • System for automatically selecting clock modes based on a state of clock input pin and generating a clock signal with an oscillator thereafter
    Patent number: 6745338
    Abstract: An apparatus comprising a circuit configured to automatically select a clock mode in response to a state of a clock input.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: June 1, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventor: Timothy J. Williams
  • Method for phase locking in a phase lock loop
    Patent number: 6744323
    Abstract: An apparatus comprising a phase lock loop (PLL) and a lock circuit. The PLL may be configured to multiply an input frequency in response to a lock signal. The lock circuit may be configured to generate the lock signal. The PLL may also be configured to select a reference frequency as (i) the input frequency when in a first mode and (ii) a divided frequency of the input frequency when in a second mode.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: June 1, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Nathan Y. Moyal, Mark R. Gehring, Russell Moen, Lawrence Ragan
  • Real-time I/O processor used to implement bus interface protocols
    Patent number: 6742071
    Abstract: A circuit that may be configured to store data and interface with an external device. The circuit may provide one or more control signals to the external device.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: May 25, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: John Boynton, Scott Swindle