Abstract: A method and a structure are provided for measuring a concentration of an impurity within a layer arranged upon a semiconductor substrate. The method may include exposing the layer and semiconductor substrate to oxidizing conditions and determining a difference in total dielectric thickness above the substrate from before to after exposing the layer and substrate. The difference may be correlated to a concentration of the impurity. In some cases, the method may include designating a plurality of measurement locations on the layer such that a concentration profile of the impurity within the layer may be determined. In some embodiments, exposing the layer and substrate may include forming an oxidized interface between the layer and the semiconductor substrate. Preferably, the oxidized interface is thicker underneath portions of the layer with a lower concentration of the impurity than underneath portions of the layer with a higher concentration of the impurity.

Abstract: A memory resident circuit cell model for characterizing an integrated circuit cell. The present invention comprises a first aggregate value representing a best case corner and a second aggregate value representing a worst case corner. In the present embodiment, the first and second aggregate value comprise a first delay representation accounting for timing variations of the cell relative to cross-coupling within the cell and a second delay representation accounting for timing variations of the cell relative to over-the-cell-routing-coupling. The first and second aggregate value further comprise a third delay representation accounting for timing variations of the cell for pin-input-capacitance and a fourth delay representation accounting for timing variations of the cell relative to delays due to near simultaneous input switching.

Abstract: A method for programming a memory device is disclosed. In one method embodiment, the present invention receives a measurement from a temperature sensor located near a non-volatile programmable memory device. Next, a transformation is accessed. Then, the measurement from the temperature sensor is processed in conjunction with the transformation to establish a programming time for a memory device as a function of a programming voltage and the temperature of the memory device. The programming voltage is then applied to the memory device for the length of time specified by the programming time during the programming pulse of the memory device to accurately program the device using an optimum amount of current.

Abstract: An integrated circuit, apparatus and method is provided for programming manufacturing information and software program information upon non-volatile storage elements on the integrated circuit. The manufacturing information includes information as to a specific processing recipe or layout used to form hardware of the integrated circuit. The software information indicates a specific revision of software used to program the integrated circuit, or a programming tool used to input the software into the integrated circuit. Combination of software and hardware is therefore embodied in non-volatile storage elements as product engineering bits. The product engineering bits can be called upon and read by the manufacturer or by the customer outside normal operation of the integrated circuit. A comparison of the hardware and software revisions will indicate possible incompatibility.

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Abstract: An asynchronous memory device includes parallel test circuitry configured to interface with a single-ended output data path of the memory device and, in some cases, to provide a measure of a slowest cell access time for the memory device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the memory device and to provide first output signals indicative of logic states of the plurality of cells; and second circuitry configured to receive the first output signals and to produce a second output signal indicative of the logic states of the first output signals therefrom. For example, the first circuitry and the second circuitry may be configured as a wired NAND and wired NOR combination. In some cases, one or more of the cells may be included within a redundant row or column of the memory device.

Abstract: According to one embodiment, the write circuitry of a content addressable memory (CAM) can include periphery circuits (102) that generate data signals (112) and write control signals (118) that connect over some distance to CAM core circuits (104). CAM core circuits (104) may include bitline write driver circuits (106), a write control circuit (108), and CAM cells (110). Write control signals (118) may include a signal surrounded by its complements and be positioned such that a routing of the write control signal is as long as the longest of the data signals (112).

Abstract: The present invention includes a circuit, system, and method for avoiding a non-desired output from a latch, and a selector circuit that is programmable to select an input to a prioritizer which, based on that input, sets the latch output to avoid a non-desired state regardless of the latching input values. The embodiments described herein are useful in forming a non-clocked latch that employs set and reset inputs, and thus, may be an SR latch. The SR latch is envisioned having either MOSFET or bipolar transistors, and can be employed either having only NMOS transistors, only PMOS transistors, or CMOS transistors. The latch also includes an improved selector circuit that is easily programmed to configure the latch in either a set-dominant, a reset-dominant, or a memory-dominant configuration based solely on the voltage values fed to the latch by the selector circuit. As such, the selector circuit of the present invention embodies an improved programmability over previous circuits.

Abstract: A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (Vss) and/or Vcc for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n+-type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n+ source subregions, or, (ii) a region that is generally annular in shape and surrounds the n+ source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.

Abstract: An apparatus comprising a first circuit and a capacitor circuit. The first circuit may be configured to generate an output signal having a frequency in response to (i) an input signal having a reference frequency and (ii) one or more adjustment signals. The capacitor circuit may be configured to adjust the frequency of the output signal. The one or more adjustment signals may provide constant current biasing of the first circuit.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to a reference impedance. The second circuit may be configured to operate in (i) a first mode in response to a first state of a second control signal and (ii) a second mode in response to a second state of the second control signal. When the second circuit is in the first mode, an output impedance of the second circuit may be adjusted in response to the one or more first control signals and the one or more first control signals may be presented at a first input/output of the second circuit. When the second circuit is in the second mode, the output impedance of the second circuit may be adjusted in response to one or more third control signals received at a second input/output of the second circuit.

Abstract: An improved clock generation circuit that utilizes a multi-phase PLL architecture is provided as well as a method for generating multiple phase outputs. The clock generation circuit can produce multiple phase outputs with the oscillator only producing approximately one-half of those multiple phase outputs. The other half of the phase outputs come from a set of delay circuits external to the oscillator. In this fashion, the oscillator can operate at relatively high frequencies yet not suffer the consequences of trying to decrease the tap-to-tap delay using additional series delay elements if numerous phase outputs are needed. Instead, one-half of the taps are provided external to the oscillator.

Abstract: An apparatus comprising a first oscillator, a second oscillator and a logic circuit. The first oscillator circuit may be configured to generate a first clock signal. The second oscillator circuit may be configured to generate a second clock signal. The logic circuit may be configured to generate an output clock signal by selecting either the first clock signal or the second clock signal.

Abstract: The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by selectively etching a dielectric layer to form a plurality of posts surrounded by trenches. The trenches are filled with a conductive material, such as a metal, deposited to a level spaced above the upper surfaces of the dielectric layer and the posts. The surface of the conductive material is then polished to a level substantially coplanar with the upper surfaces of the dielectric layer and the posts. Advantageously, the polish rate of the conductive material above the trenches is substantially uniform. In this manner, the topological surface of the resulting interconnect level is substantially void of surface disparity.

Abstract: A circuit for generating an output signal, such as a subword line signal, to one or more memory cells of a memory. In one embodiment, the circuit includes four transistors each with a separate select line. In one example, a first switch is provided and has an input coupled with a global word line input signal; a second switch has an input coupled with the output of the first switch at an output node; a third switch has an input coupled with the global word line input signal and the output of the third switch being coupled with the output of the first switch at the output node; and a fourth switch having an input coupled with the output of the third switch at the output node and the output of the fourth switch is coupled with the output of the second switch.

Abstract: A method for relative pin placement guidance, comprising the steps of (A) placing a plurality of pins to form a pinout in response to a first design, a second design and an attribute and (B) determining one or more placement constraints, one or more groups of the pins, and routing of the pins in response to the attribute.

Abstract: An integrated circuit comprising a memory and a logic circuit. The memory may comprise a plurality of storage elements each configured to read and write data in response to an internal address signal. The logic circuit may be configured to generate a predetermined number of the internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) one or more control signals. The generation of the predetermined number of internal address signals may be non-interruptible.

Abstract: A lead frame assembly includes one or more lead frames each defining a plurality of package locations organized in rows and columns. An injection molding system includes a plurality of culls, each cull being connected to the frame(s) through a plurality of subrunners. Each subrunner delivers molding compound from one of the culls to a respective column of package locations. A plurality of through gates are disposed between adjacent package locations within each column, each through gate supplying molding compound from one package location to a next adjacent package location within the column, each package location being filled with molding compound in turn from the preceding package location. The need for subrunners between adjacent columns of package locations is eliminated, allowing a higher density of package locations within the lead frame(s), reducing materials and labor costs, and increasing manufacturing productivity.

Abstract: An embodiment of the present invention provides a method and apparatus that effectuates a direct functional interface directly with individual constituent subcomponents of the internal die component, or with particular circuit nodes or conductive trace locales of the surface mount package, without high frequency signal degradation or other electrical problems. An embodiment of the present invention also provides a method and apparatus that effectuates testing access, directly to the internal die component of the surface mount package or to a particular circuit node or conductive trace locale of the surface mount package, enabling performance evaluation and system debugging. Further, an embodiment of the present invention provides a method and apparatus that effectuates integration of surface mount package with an opto-electronic package. Further still, an embodiment of the present invention provides a method and apparatus that achieves these advantages with minimal cost.

Abstract: A programmable logic device comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first plurality of clock signals in response to (i) one or more input clock signals and (ii) a configuration signal. The second circuit may be configured to generate a second plurality of clock signals in response to (i) said first plurality of clock signals and (ii) said configuration signal. The third circuit may be configured to present a third plurality of clock signals selected from (i) said one or more input clock signals, (ii) said second plurality of clock signals in response to said configuration signal.