Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to precisely generate a reset when the apparatus is in a first operational mode. The second circuit may be configured to generate the reset when the apparatus is in a second operational mode.

Abstract: An interface coupled to a multiqueue storage device and configured to interface the multiqueue storage device with one or more handshaking signals. The multiqueue storage device and the interface may be configured to transfer variable size data packets.

Abstract: An apparatus comprising a reference generation circuit and a modulator. The reference generation circuit, may be configured to generate a first one or more reference voltages and a second one or more reference voltages. The modulator may be configured to present an output signal in response to an input signal, the first reference voltages and the second reference voltages. A gain between the output signal and the input signal may be set by a capacitor ratio in said modulator.

Abstract: A circuit comprising a plurality of communication devices each configured to receive and transmit one or more data packets in response to one or more control signals and a control circuit configured to generate the one or more control signals in response to the one or more data packets.

Abstract: A circuit comprising a phase detector/correction circuit, at least one column of memory cells, a control circuit and a sense amplifier. The control circuit may be configured to read a sequence from the memory cells in a predetermined order and present a first output signal. The sense amplifier may be configured to present a periodic signal in response to the first output signal.

Abstract: One aspect of the present invention concerns an apparatus comprising a circuit that may be configured to present a connection signal. The connection signal may be configured to automatically disconnect and reconnect a peripheral device from a host in response to one or more errors. In another aspect of the present invention the connection signal may be configured to shift a configuration of a peripheral device in response to one or more errors.

Abstract: A method for receiving and transmitting one or more data packets comprising the steps of (A) receiving and transmitting the one or more data packets in response to one or more control signals and (B) generating the one or more control signals in response to the one or more data packets.

Abstract: A method of making a semiconductor structure, includes annealing a structure in a deuterium-containing atmosphere. The structure includes (i) a substrate, (ii) a gate dielectric on the substrate, (iii) a gate on the gate dielectric, (iv) an etch-stop layer on the gate, and (v) an interlayer dielectric on the etch-stop layer.

Abstract: An apparatus comprising a plurality of devices configured to store and present data to a plurality of queues. Each of the plurality of devices may be configured to receive (i) one or more first control signals configured to control data transfer and (ii) one or more second control signals to configure the plurality of queues. A particular one or more of the plurality of devices may be selected in response to one or more device identification bits.

Abstract: A method for creating a specification for a device. The method may include the steps of (A) creating a base class having a first rule set for a programmable die, (B) filtering a definition for the device against a second rule set to present a result in response to creating, and (C) polymorphing the base class according to the result to present the specification for the device in response to filtering.

Abstract: A method is provided for fabricating a device, which includes device components and spacings that may each have a final dimension that is smaller than a minimum dimension obtainable by a photolithography process used to form the device components. In particular, the method may include patterning an upper layer of the semiconductor topography using the photolithography process to form a device mask having dimensions substantially equal to or greater than the minimum dimension. The method may further include trimming the device mask and forming a semiconductor structure in alignment with the trimmed device mask. In addition, the method may include patterning the semiconductor structure to form device components and spacings therebetween. In general, patterning the semiconductor structure may include tapering a first layer of the semiconductor structure and removing an exposed portion of a second layer of the semiconductor structure.

Abstract: A pendulum motor having a stator and a cantilever beam moveable by an electrostatic force to predetermined positions relative to a supporting structure. A micro electro mechanical system (MEMS) mechanism is formed on a semiconductor substrate using process steps that are completely compatible with current CMOS technology. A cantilever beam is fixed at one end to a structural layer and an electrode arrangement that provides an electrostatic field across a gap between the beam and a stator. A force between the beam and the stator generated by the electrostatic field results in movement of the free end of the beam relative to the stator. The free end of the beam may then be displaced by a predetermined amount from an equilibrium position and held in place by means of an applied electrostatic field. Movement of the free end of the beam is in a plane parallel to the surface of the support structure and it may follow either a circular or a non-circular path.

Abstract: An apparatus comprising one or more memory blocks in a programmable logic device. The memory blocks may be configured as content-addressable memory having arbitrarily adjustable tag and data widths.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to receive a first input signal and a second input signal and present a first signal and a second signal. The second circuit may be configured to present a first output signal in response to the first input signal, the first signal and the second signal. The third circuit may be configured to present a second output signal in response to the second input signal, the first signal and the second signal.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first intermediate signal in response to a first differential signal and (ii) a second intermediate signal in response to a second differential signal. The second circuit may be configured (i) to generate one or more output signals in response to a relative arrival time of the first and second intermediate signals and (ii) to clamp a later arriving one of the first and second intermediate signals to a predefined voltage level.

Abstract: Methods and apparatus for remotely controlling an ATA device via a packet-based interface are disclosed. In one implementation, a remote host constructs command blocks corresponding to the ATA register-delivered commands that it would like executed. These command blocks are packetized and transported to a packet-to-ATA format bridge. At the bridge, each command block is parsed, and appropriate ATA read or write register commands are performed. The bridge performs requested data transfers via the packet-based interface. This embodiment can allow a non-ATAPI ATA device to connect externally to a host computer, e.g., via a USB plug-and-play packet interface. This can provide inexpensive and portable mass storage capability that does not require internal mounting or external routing of the short ATA cables that are intended for internal use only.

Abstract: A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) enabling the background operations in one or more sections of the memory array when one or more control signals are in a first state and disabling the background operations in one or more sections of the memory array when the one or more control signals are in a second state and (ii) generating the one or more control signals in response to an address signal.

Abstract: A NAND stack array (95′) is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.

Abstract: A method and apparatus for verification of a semiconductor device design is disclosed that includes the determination of electrical distance for shapes of a design of a semiconductor device. In the present embodiment, the method includes, for each shape to be analyzed, growing from a seed disposed within a boundary shape to be analyzed. After each new growth step, a frontier edge or a frontier polygon is generated. No frontier edges or frontier polygons result from growth steps relating to boundary shapes that have fully traversed. Therefore, as each smaller shape is traversed, growth within the traversed shape is discontinued (no frontier edges or frontier polygons result). Thus, the growth regions of smaller shapes that have been traversed drop out, and are not included in subsequent growth steps, advantageously reducing memory requirements and run-time.

Abstract: One embodiment of the present invention is a programmable clock architecture for a microcontroller that provides multiple different clocking signal frequencies that may be utilized by one or more programmable logic blocks of the microcontroller. In this manner, the clocking architecture enables the programmable logic blocks to perform a wider variety of functions because they have access to a wider variety of clock signal frequencies. Specifically, the clocking architecture of the present embodiment includes a plurality of clocking sources. For example, the output clocking signal of one of the clock oscillators is divided down to different smaller frequencies and also multiplied to provide more frequencies that may be utilized by the programmable circuit blocks and processor of the microcontroller.