Abstract: A method and architecture for providing signal paths between a programmable logic core and a fixed function core comprising the steps of (a) coupling one or more first signals between the fixed function core and an interface block configured to couple the fixed function core and the programmable logic core and (b) coupling one or more second signals between the interface block and the programmable logic core.

Abstract: According to one embodiment, a content addressable memory (CAM) (100) can include a number of CAM entries (102-0 to 102-n) and corresponding status stores (106-0 and 106-n). Match indications from the CAM entries (102-0 to 102-n) and status information from status stores (106-0 and 106-n) can be supplied to a switching circuit (108). Status information can indicate if an entry stores valid or invalid data. In one mode of operation, the switching circuit (108) can provide match indication values on a number of switch outputs (SW0 to SWn). In another mode of operation, the switching circuit (108) can provide status information on a number of switch outputs (SW0 to SWn).

Abstract: A method for placement and manipulation of logic equations of a device design, comprising the steps of (A) identifying one or more logic equations of the device design with placement problems, (B) identifying one or more candidate equations of the logic equations with placement problems, and (C) re-synthesizing the one or more logic blocks of the candidate equations without adding latency to the device design.

Abstract: A method for depositing a metal layer on a substrate includes the steps of depositing a first metal layer at a first deposition temperature; depositing a second metal layer on the first metal layer at a second deposition temperature higher than the first deposition temperature; reducing at least one of a growth rate and a temperature of at least the second metal layer; and depositing a third metal layer on the second metal layer. Preferably, the growth rate is reduced substantially to zero and the temperature is reduced to a point below which the second metal layer ceases to flow. By interrupting the processing the metal layer prior to the third metal layer forming step by the reducing and/or cooling step, the formation of whiskers and other similar thermal stress-induced defects is suppressed or inhibited, resulting in a substantially smooth and substantially defect free metal layer.

Abstract: An apparatus comprising one or more input circuits. The input circuit may be configured to generate an output signal in response to (i) an input signal and (ii) an input threshold. The input threshold may be set in response to a control input.

Abstract: A circuit comprising a memory and a logic circuit. The memory may be configured to read and write data in a plurality of memory queues to/from a write data path and a read data path in response to (i) a first and a second select signal and (ii) a first control signal. The logic circuit may be configured to generate (i) the first and second select signals and (ii) the control signal in response to one or more signals received from a read management path and/or a write management path.

Abstract: An apparatus configured to read and write data in a plurality of memories. The plurality of memories may be configured to store and present the data in response to (i) a write data path and (ii) a read data path. One of the plurality of memories may be configured to control the remainder of the plurality of memories in response to one or more write signals and (ii) one or more read signals.

Abstract: A device generally comprising a memory array and a burst sequence generator. The memory array may be configured to store data. The burst sequence generator may be configured to generate a burst sequence in response to address information received by the device. The burst sequence may be configured to identify a plurality of locations for storing data in the memory array. The device may have a maximum operating current of 50 milliamps and/or a maximum standby current of about 25 microamps.

Abstract: The invention provides a method and system for memory management, in which at least some individual nodes in a hybrid trie are striped across a set of pipelined memories. Memory management is performed for a hybrid trie including both branch-search nodes and leaf-search nodes and maintained in a sequence of pipelined memories. The method provides for insertion and removal of data elements within the hybrid trie and for storing at least some of the nodes in stripes across a sequence of the memories. Memory management is performed for the leaf-search nodes, by selecting stripes from the possible subsequences of those memories, that are suited to pipelined operations performed on the memories. In a preferred embodiment, an invariant condition is maintained for families of those stripes, in which exactly one cell block is labeled “sparse” and that cell block is used in techniques for allocation and de-allocation of entries.

Abstract: The invention concerns a method for forming metallization and contact structures in an integrated circuit. The method involoves the steps of etching a trench in the trench dielectric layer a trench dielectric layer of a composite structure containing a semiconductor substrate comprising an active region, a gate structure thereover, and dielectric spacers adjacent to the gate structure, a contact dielectric layer; and the trench dielectric layer; etching the contact dielectric layer under conditions which do not damage the gate structure to form a first contact opening that exposes a region of the semiconductor substrate; and depositing a conductive material into the contact opening and the trench.

Abstract: A system and method for graphically displaying modules and resources within a chip design software application. The system and method provide a graphical interface which relate both a module and the associated resource. This graphical interface utilizes highlights of both the module and the associated resource in patterns, grayscales, or colors to graphically illustrate the relationship between the module and the associated resource. The system and method also provide a graphical interface which illustrates a fixed group and unfixed group of resources associated with a particular module. The unfixed group of resources can be iterated to a next possible location on the chip that would satisfy the requirements of the associated module. Any fixed group of resources can be selected as the unfixed group by selecting that group of resources.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of signals in response to one or more input signals. The second circuit may be configured to generate one or more control signals in response to said plurality of signals. The one or more control signals may control one or more non-logic features.

Abstract: A circuit for providing substantially a constant delay of an electrical signal that compensates for voltage, temperature and process variations includes an inverter. A delay cell has an output that is coupled to the inverter. The delay cell includes a charge transistor coupled to a capacitor. A control circuit has an output that is coupled to a gate of the charge transistor. The output has a voltage that is proportional to a trip voltage of the inverter. The delay cell also has a discharge transistor. The control circuit contains a second output that is coupled to a gate of the discharge transistor. The second output has a voltage that is also proportional to the trip voltage of the inverter.

Abstract: An apparatus for initializing a default value of a queue. The apparatus comprising a memory section having a first storage element and a second storage element. The apparatus may be configured to pass the default value and initialize the default value of the queue without writing to the memory section.

Abstract: Energy is applied to a portion of a conducting body. In preferred embodiments, relative motion between the conducting body and the energy source is created such that the energy source moves along a thermal diffusion front, thereby enhancing the thermal diffusion front in the direction of the relative movement. The energy is preferably applied in a portion of the conducting body with higher thermal mass and the enhanced thermal diffusion front is directed toward a portion with lower thermal mass. The lower thermal mass portion expands, thereby creating fissures in surrounding material, then melts, flows through the fissures and contacts another conductor, thereby forming a conductive link.

Abstract: A biasing circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a first bias signal and a second bias signal. The second bias signal may be defined by a threshold voltage and a first resistance. The second circuit may be configured to generate a third bias signal in response to the first and the second bias signals and a second resistance. The third bias signal may have a magnitude that is linearly proportional to absolute temperature (PTAT) and be configured to vary a refresh rate of a memory cell in response to changes in temperature.

Abstract: An apparatus comprising an analog delay line and a control circuit. The analog delay line may be configured to generate an output signal in response to an input signal, a first control signal, and a second control signal. A phase of the output signal may be (i) coarsely adjustable with respect to the input signal in response to the first control signal and (ii) finely and continuously adjustable in response to the second control signal. The control circuit may be configured to generate the first and the second control signals in response to the input signal and the output signal.

Abstract: An apparatus comprising a first bus, a second bus, a memory and one or more interconnections. The memory may be connected to the first bus and the second bus and may be configured to transfer data over the first bus and the second bus. The one or more interconnections may be connected between one or more data lines of the first bus and the second bus to control a bit-width of the first and second buses.

Abstract: The invention enables a layer of metal to be formed on a substrate with few or no voids formed in the layer, with increased throughput and without raising the temperature of the substrate to a level that may damage the substrate. A layer of metal can be formed on a substrate using a cold deposition step followed by a hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit metal over the entire surface on which the metal layer is to be formed. In the hot deposition step, further metal is deposited while the substrate is rapidly heated to a target temperature. The rapid heating quickly mobilizes the atoms of the deposited metal, making the deposited metal far less susceptible to cusping and voiding than has been the case with previous methods for depositing a metal layer on a substrate that include a cold deposition step followed by a hot deposition step.

Abstract: An interface coupled to a multiqueue storage device and configured to interface the multiqueue storage device with one or more handshaking signals. The multiqueue storage device and the interface may be configured to transfer variable size data packets.