Abstract: A method is provided for processing a semiconductor topography. In particular, a method is provided for forming wells of opposite conductivity type using a single patterned layer. In addition, the method may include forming a silicon layer having first and second portions of opposite conductivity type. The formation of the silicon layer may include the use of the single patterned layer or an additional patterned layer. In addition, the method may include forming channel dopant regions within the wells of opposite conductivity type. The formation of such channel dopant regions may be incorporated into the method using the one or two patterned layers used for the formation of the wells and doped silicon layer. Such a method may include introducing impurities at varying energies and doses to compensate for the introduction of subsequent impurities. As such, the method may form a dual gate transistor pair, including n-channel and p-channel transistors.

Abstract: A transistor includes a non-self-aligned gate-terminal junction in a substrate having a relatively thick oxide layer disposed between a gate region and a terminal region and a relatively thin oxide layer disposed between the gate structure and the substrate. The terminal region may be the drain region of the transistor and it may include a buried N+ region within the substrate. The transistor may be formed in a p-well. Further, the transistor may also include a self-aligned gate-terminal junction between the gate structure and a source region. In a further embodiment, a transistor fabrication method includes forming an active area in a substrate and implanting an N-type impurity into a first terminal region of the active area. An oxide layer is differentially grown over the active area so that the oxide layer has a first thickness over the first terminal region and a second thickness over the remaining portion of the active area.

Abstract: A circuit comprising a memory and a control circuit. The memory may be configured to (i) hold one or more packets of information and (ii) send the held packets of information in response to one or more control signals. The control circuit may be configured to generate the one or more control signals.

Abstract: An apparatus for implementing memory initialization comprising a logic circuit configured to present an address to a memory. The memory initialization may occur as a background process.

Abstract: A method of forming a localized oxidation having reduced bird's beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper between about 10° and about 75° as measured from the vertical axis of the recess opening and then growing field oxide within the tapered recess opening for forming the localized oxidation.

Abstract: An apparatus comprising a first circuit configured to generate a first portion of an output signal in response to (i) a first supply voltage and (ii) a pullup signal and a second circuit configured to generate a second portion of said output signal in response to (i) a second supply voltage and (ii) a pulldown signal, wherein said first and second circuits are implemented with transistors that normally can only withstand said second supply voltage.

Abstract: The present invention is directed to a flexible converter suitable for providing a routing function. A flexible converter of the present invention may provide a desired output utilizing a variety of methods, systems and apparatus without departing from the spirit and scope of the present invention. A routing apparatus may include a converter, at least one comparator and a controller. The converter is capable of providing an output supply from an input supply coupled to the converter, the output supply capable of routing between a first output and a second output. At least one comparator is coupled to the output supply of the converter, the comparator capable of measuring at least one power characteristic of the first output and the second output to a first electrical device and to a second electrical device.

Abstract: An apparatus comprising one or more output circuits each configured to configure a pad as either an input/output pad, a power pad, or a ground pad in response to a plurality of configuration inputs.

Abstract: A lead frame includes a first side rail, a second side rail spaced apart from the first side rail, a center rail disposed between the first side rail and the second side rail, and a plurality of package locations. Each package location includes a first and a second die attach paddle. The first die attach paddle supports a first side of a semiconductor die and is coupled only to the first side rail or to the second side rail. The second die attach paddle supports a second side of the semiconductor die and is coupled only to the center rail. The first and second die attach paddles are separate and unconnected to each other and may be generally circular in shape. An aggregate surface area of the first and second paddles may be less than about 25 percent of a surface area of the semiconductor die.

Abstract: An apparatus comprising one or more input/output circuits that may be configured as (i) high voltage tolerant in response to a first state of a control input and (ii) a clamp to a power supply voltage in response to a second state of said control input.

Abstract: A method for reading a position of a wiper on a potentiometer, comprising the steps of (A) charging a capacitor connected to a wiper terminal of the potentiometer, (B) discharging the capacitor through a particular terminal of the potentiometer, (C) measuring a first time taken to discharge the capacitor from a first voltage to a second voltage, (D) recharging the capacitor, (E) discharging the capacitor through another particular terminal of the potentiometer, (F) measuring a second time taken to discharge the capacitor from the first voltage to the second voltage, (G) reading the position of the wiper by calculating a ratio of the times measured in steps (C) and (F).

Abstract: A method for writing and reading in-band information to and from a single storage element, comprising the steps of (A) receiving the in-band information, (B) storing data in either (i) a port information register when in a first state or (ii) a memory element when in a second state and (C) storing subsequent data in the memory element. The first state and the second state may be dependent upon a block position of the in-band information.

Abstract: The present invention relates to an input/output node in an electronic device which comprises an input/output pin, a plurality of programmable pull-up resistors and a plurality of programmable pull-down resistors. Each of the pull-up and pull-down resistors, or a combination of them, can be activated by turning on or off n-MOS and p-MOS transistors with logic contained in a mode register. The pull-up and pull-down resistance can be implemented by the inclusion of a resistor in series or by utilization of the innate resistance of the MOS-FET transistor, itself. The resistances can be strong, medium, or weak, depending on the needs of the circuitry. One advantage of such control over drive strength is the ability to transmit or receive data in virtually any electronic environment. Another advantage is the ability to reduce voltage ramp-rates, which reduces high frequency harmonics and the attendant electromagnetic interference.

Abstract: A system for facilitating packet data flow among stations on a data network and the associated method are disclosed. The system comprises queue managers that further comprise a free queue manager, an enqueue controller, a multicast queue manager, and a port queue manager. The free queue manager provides a mechanism to monitor the number of free buffers remaining in an external memory. The enqueue controller arbitrates between requests for enqueuing from the ports. The multicast queue manager maintains a multicast queue linked list and manages multicast queue entries to the list. The port queue manager manages output queues of each of the output ports and ensures that a packet is correctly routed to the appropriate ports for subsequent delivery. With the queue manages working in synchronization, an inbound packet can be routed to ports designated by the packet for delivery within a minimum time.

Abstract: An approach for testing an erasable programmable read-only memory (EPROM) cell for a threshold voltage is provided. A voltage lower than a source voltage that is associated with a read operation is applied to the gate of the EPROM cell. A signal is read out from the EPROM cell when the voltage is applied to the EPROM cell. The signal is used to calculate the threshold voltage of the EPROM cell.

Abstract: An apparatus comprising an output connected to a plurality of inputs through a tree of connections. Each of one or more branches of the tree may be equidistant between the output and each of the plurality of inputs.

Abstract: An apparatus comprising one or more configuration blocks. The configuration blocks (i) may comprise a number of configuration elements and (ii) may be configured to initiate reading or writing of the configuration elements in response to a control input.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present (i) a pump up signal in response to a reference signal and a reset signal and (ii) a pump down signal in response to an input signal and the reset signal. The second circuit may be configured to (i) switch a pull up signal in response to the pump up signal, (ii) switch a pull down signal in response to the pump down signal, and (iii) present the reset signal in response to switching the pull up signal and the pull down signal.

Abstract: An embodiment of an amplifier circuit including a power supply node and an output node is adapted to provide, during operation, an output node voltage ranging to within 0.2 volts of a power supply voltage used during the operation. An embodiment of the circuit includes a differential first stage coupled to the power supply node and providing a pair of first stage outputs for coupling to a differential second stage. In a method of providing an output voltage near the power supply voltage of an amplifier, a first stage output voltage ranging to within a transistor turn-on voltage of the power supply voltage is produced. The first stage output voltage may further be coupled to a second stage of the amplifier, where the coupling may modulate a current flow through a first pair of cascaded transistors. An output node of the amplifier may be arranged between the pair of transistors and the power supply voltage node.

Abstract: An apparatus comprising a memory, a first circuit and a second circuit. The memory may be configured to read and/or write data to/from one or more ports. The first circuit may be configured to bi-directionally transfer data between an external I/O bus and an internal I/O bus in response to a plurality of control signals. The second circuit may be configured to generate the plurality of control signals in response to a plurality of input signals. The data signals generated by the two circuits may allow reduced bus size access in one or more word formats.