Abstract: A NAND gate including a pull-down circuit coupled to a pull-up circuit. The NAND gate is configured to drive an output signal to a high logic state at a substantially uniform slew rate regardless of the number of input signals that are in a low logic state. The pull-up circuit may include a plurality of load circuits each coupled to a corresponding one of the plurality of input signals, and a plurality of transistor circuits each comprising a plurality of transistors coupled in parallel with each other and coupled to a corresponding one of the plurality of input signals or a complement of a corresponding one of the plurality of input signals. The plurality of load circuits and the plurality of transistors may each include a p-channel MOS (PMOS) transistor. The NAND gate may be incorporated into a decoder of a synchronous or asynchronous input path circuit to generally reduce the setup and hold time window of the input path circuit.

Abstract: A circuit for enabling and disabling generation of an output clock signal is disclosed. The circuit includes a PLL lock detect circuit that generates an active lock control signal when an output reference signal of a phase lock loop (PLL) circuit is phase locked relative to an input reference signal to the PLL. The output reference signal of the PLL, and the lock signal from the lock detect circuit, are both provided to a clock enable circuit. The clock enable circuit includes a negative edge-triggered D-type flip-flop and a two-input AND gate. The lock signal is applied to the D-input of the flip-flop, while the clock signal is applied to the clock input of the flip-flop. The lock signal is generated asynchronously relative to the input clock signal. Therefore, the flip-flop samples the lock signal on each falling edge of the clock signal so as to synchronize the lock signal relative to the input clock signal.

Abstract: A register using a single pin to provide two or more control signals (e.g., clock and data signals). The present invention decodes a three state input waveform to generate a clock/write signal and uses a three state clock waveform to generate a clock/read data signal. The present invention generally comprises a three-level receiver, a latch and an output driver to form a one-pin bidirectional interface used with a shift register. To write, the interface converts a three-level input signal into separate clock and data signals which drive the shift register. To read, the interface converts a bi-level input signal into a three-level output signal representing the output of the shift register. As a result, the present invention allows the programming of a device such as an erasable programmable read only memory (EPROM) in a clock chip while utilizing the fewest number of pins.

Abstract: A memory device includes a random access memory (RAM) cell accessible through a RAM wordline and coupled between first and second bitlines; a read only memory (ROM) cell accessible through a ROM wordline and having an output coupled to the first bitline and an input configured to receive a first voltage signal; and a reference voltage generator having a first input coupled to the first bitline, a second input configured to receive the first voltage signal, and an output coupled to the second bitline. The memory device may further include a bitline load having an output coupled to the first bitline. A virtual ground driver configured to produce the first voltage signal may be coupled to the input of the read only memory cell. Further, column select pass gates configured to be under the control of a logic signal and having a first input coupled to the first bitline, a second input coupled to the second bitline, a first output and a second output may be provided.

Abstract: A method and apparatus for greatly simplifying the circuitry needed to handle the bubbleback situations in FIFO memories includes an additional row of cells added to the memory array. By adding an extra row of memory cells, the read and write pointer are only on the same row when the FIFO is operating near the empty boundary or in fallthrough mode.

Abstract: A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

Abstract: An improved I/O cell is disclosed which includes a combined p-channel and n-channel transistor pullup configuration. In particular, such combination is connected in series between the chip operating voltage V.sub.cc, and the I/O cell output pad. The n-channel transistor is biased substantially continuously on its gate terminal with a pumped voltage from a charge pump, which permits it to pass voltages up to and including V.sub.cc. The p-channel transistor operates in its normal fashion, controllable via a pullup select signal applied to its gate terminal to pull the pad high. During normal operation, the n-channel transistor is always ON, thus reducing the substantial dynamic current drawn from the charge pump. The voltage appearing on the pad is fed back to a second n-channel transistor. When the voltage on the pad exceeds V.sub.cc for example, a 5 volt signal when V.sub.cc is 3.

Abstract: The present invention provides a circuit and method for generating a parity bit and checking the parity of data words positioned in the read data path of a memory device or buffer. The parity check mode can detect errors. The parity generation mode generates EVEN or ODD parity as an additional bit. Other devices in the system may generally be configured to accept either EVEN or ODD parity. The parity generation and checking circuit can detect errors in both the data input to the buffer as well as errors created in the storage of the data by the buffer.

Abstract: A circuit comprising a switch section configured to generate a first and second control signal. A pull section may receive the first and second control signals to generate an output. A capacitor may be coupled between the switch section and the pull section for coupling the output to the switch section.

Abstract: The present invention provides a circuit and method using a floating PMOS transistor connected in series between the transistors of an input invertor. The floating PMOS transistor may be used to control the amount of current through the transistors. The gate of the floating PMOS transistor may be connected through a reference line to a duplicate of the input inverter stage. The duplicate stage is generally located in a reference block and fed with a stabilized reference voltage. Each couple (formed by the buffers input stage and the duplicate stage) functions as a differential comparator, which checks the input voltage against the reference voltage and rejects the power supply voltage variations which are perceived as a common-mode noise signal. The supply current is fixed by the reference voltage which reduces power consumption at high input voltages and high supply voltages.

Abstract: A circuit for presenting one or more current source outputs which may be used to optimize the interface between optical components in a computer system. The multiple currents may be independently varied in each particular component to provide a current adjustment for proper functioning of a wide variety of LEDs and photo transistors. As a result, a dynamic optimization of the devices is provided. Since the present invention allows a wide variety of optical components to be used, the overall cost of implementing the device may be reduced.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: A circuit includes a band-gap reference circuit and a start-up circuit coupled between an output and an input of the band-gap reference circuit. When the output of the band-gap reference circuit is below a start-up voltage threshold, the start-up circuit provides a first voltage at the input of the band-gap reference circuit which, in turn, causes the band-gap reference circuit to produce a desired voltage at the output. When the desired voltage has been reached, i.e., a voltage corresponding to the start-up voltage threshold, the start-up circuit turns off and does not interfere with the normal operation of the band-gap reference circuit. The start-up circuit may include first circuitry configured to produce a first voltage if a voltage signal at the output of the band-gap reference circuit is below the start-up voltage threshold.

Abstract: A circuit comprising a generation circuit for providing a clock signal. A number of compensation circuits may receive the clock signal and may present essentially simultaneously a compensated clock signal at their outputs. The compensated clock signals are generally presented to a plurality of synchronous external devices.

Abstract: The present invention significantly lowers the continuous write cycle ICC, thus lowering the overall ICC specification, for multi-port (and single port) memory devices without significant changes in ICC.sub.WR and ICC.sub.RR currents. In one embodiment, a circuit for the generation of a Write Data select signal (i.e., TTL.sub.-- SEL) according to the present invention employs a unique "write power-down" delay (t.sub.WPD) which is a function of "CE+WE" (chip select and write enable) and incorporates the delay into the generation of the Write Data select signal, TTL.sub.-- SEL. The delay t.sub.WPD is provided by a delay device and is preferential. That is, a delay is provided when the internal write data select signal, i.e., TTL.sub.-- sel (which is a function of "CE+WE"), transitions from logic "1" to a logic "0", but no delay is produced when TTL.sub.-- sel transitions from a logic "0" to a logic "1".

Abstract: The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size.

Abstract: An output buffer circuit of a semiconductor memory device can produce multiple output buffer drive strengths. An electronic system including a memory device in which such an output buffer circuit is implemented can include a mechanism for enabling the output buffer drive strength to be easily selected by a user of the memory device (such as an assembler of an electronic system including the memory device) from the multiple possible drive strengths. The invention thus enables a memory device to be easily configured to have an output buffer drive strength that is compatible with a wide variety of electrical loads to be driven by the output buffers of the memory device.

Abstract: A self-resetting logic stage provides for a relatively faster propagation of pulse signals and for relatively less power consumption. For a self-resetting logic stage in a digital logic path of successive logic stages, a forward path creates the forward edge for an output pulse signal and a reset path creates a reset or trailing edge for the output pulse signal. The propagation delay for the reset path may be increased for successive stages in the logic path to minimize or avoid overlap current. As the increased propagation delay increases the width of a pulse signal as the pulse signal propagates from stage to stage, logic stages in the logic path may be configured to reduce the width of the pulse signal, for example when the pulse signal approaches a width that may limit the cycle time for the logic path. Logic stages in the logic path may also be configured to provide for relatively quicker reset recovery to minimize any increase in cycle time.

Abstract: A conducting trench in a dielectric layer can function as both (a) a plurality of contacts and (b) an interconnect in a semiconductor device. The conducting trench may be made by depositing a conductor in a trough formed in a dielectric layer of the device.

Abstract: A method and apparatus for writing data onto the read bitline when a FIFO buffer memory is nearly empty that includes circuitry detecting when a memory is nearly empty, when the read pointer and the write pointer are on the same line with the read pointer behind the write pointer. Another circuit writes data onto the read bitline as the data is written into the buffer memory.