Abstract: A single ended simplex dual port memory cell is described. One port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

Abstract: An asynchronous flag generator for generating an asynchronous flag having a minimum defined active pulse length. The asynchronous flag generator comprises an arbitrary length flag generator for generating an arbitrary length status flag signal from at least two asynchronous signals, one being a set flag signal and the other being a clear flag signal. A minimum pulse generator for generating a minimum pulse having a predefined pulse length upon initiation of the set flag signal. Combinational logic combines the arbitrary length status flag with the minimum pulse to generate an asynchronous status flag with a defined minimum active pulse length.

Abstract: The present invention concerns an improved charge pump. The charge pump efficiently charges a voltage signal while reducing its power consumption. The charge pump includes at least one diode configured to receive a voltage signal. Coupled to the diode(s) is at least one capacitive device that is capable of coupling charge onto the diode(s). For one embodiment, the capacitive device provides a constant capacitance to more efficiently charge the voltage signal. The charge pump also includes an oscillating circuit that is capable of providing each capacitive device with an oscillating signal that alternates between a first voltage level and a second voltage level at a predetermined frequency. The oscillating circuit includes an odd number of N inverters coupled in a ring wherein an output of the Nth inverter is coupled to the input of the first inverter.

Abstract: A method for programming or testing a CPLD using an additional read register. In one embodiment, the method comprises: instructing the CPLD in one instruction to load program data, load address information and program the program data into a memory location having an address defined by the address information; loading the program data into a first data storage element and the address information into an address storage element; programming the program data into the memory location; instructing the CPLD to read verify data from the memory location; and capturing the verify data into a second data storage element. The second data storage element comprising a read registers. The novel method further comprises comparing the verify data with the program data. The verify data and the program data may be compared within the CPLD or the verify data may be output from the CPLD and compared with the program data externally.

Abstract: The invention concerns an asynchronous state machine with a programmable tSKEW which may be used to generate a half-empty and half-full flags in a synchronous FIFO buffer. The present invention may reduce the delay associated in producing the half-full or half-empty flags from a typical eight gate delays, to as little as no gate delays. The reduction may be accomplished by using a first state machine which can make an internal flag go low, or active, and a second state machine which can make the internal flag go high, or inactive. The functioning of the first and second state machines may be controlled by a blocking logic. The output of each of the state machines may be stored in a latch. The output of the latch may be presented to an input of the blocking logic, which may be used by the blocking logic to control the activity of the state machines.

Abstract: A driver circuit is presented which can transition between output voltage levels at a high switching speed. The preferred output driver is a PECL driver having both a correction circuit portion and a drive circuit portion. The correction circuit senses changes in the base-to-emitter forward bias voltage V.sub.BE of drive transistors within the drive circuit. Thus, any change in performance of those drive transistors is replicated in the correction circuit, which then produces a compensating current. The compensating current is modulated by a reference voltage value, and mirrored to the drive circuit. The drive circuit includes not only differential input transistors and differential drive transistors, but also a resistor coupled to the base terminal of each drive transistor. The resistor receives the compensating current which then offsets any change in voltage level (V.sub.OH or V.sub.OL) produced at the output of the drive transistors.

Abstract: A state machine design which can be used to realize extremely short flag generation delays. The present invention also realizes the benefit of having an extremely high MTBF. The present invention generates a set of next state variables that are generated from a combination of three previous state variables and three additional inputs representing a logical "OR" of a read half-full and write half-full flag WRH, an external write clock input, and an external read clock input. The next state variables are derived from a product of the previous state variables, a complement signal of the previous state variables, and the signal WRH. The half-full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal.

Abstract: A slew rate control circuit to control output slew rate according to a programmable reference signal. A slew rate control circuit limits the slew rate of a plurality output buffers according to a signal received from a programmable slew rate control reference.

Abstract: A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) a detect signal and (ii) a transition of the address signal.

Abstract: The state of a memory cell is stored by selectively imbalancing threshold voltages of storage elements of the memory cell. The threshold voltages may be selectively imbalanced by pulsing the supply voltage for the memory cell from an operating voltage level to a programming voltage level. This may be accomplished by raising the supply voltage from the operating voltage level to the programming voltage level for a period of time sufficient to store the state of the memory cell by monitoring the leakage current from the programming voltage level such that it just falls below a preestablished limit. Alternatively, the supply voltage may be repeatedly toggled between the operating voltage level and the programming voltage level for fixed time intervals until the state of the memory cell is stored. The number of toggling operations may be determined by monitoring the leakage current such that it just falls exceeds a predetermined limit.

Abstract: A circuit and method for framing an input data stream to a periodic signal. The circuit comprises a register circuit, a logic circuit and a multiplexor circuit. The register circuit may be configured to store information and to present a first and second output in response to (i) the input data stream and (ii) the periodic signal. The logic circuit may be configured to (i) detect a predetermined bit sequence and (ii) present a control signal in response to the information stored in the register circuit. The multiplexor circuit may be configured to present one or more multiplexed signals comprising the first and second outputs of the register circuit in response to the control signal.

Abstract: A buffer comprising a plurality of storage elements, a write pointer configured to indicate a particular storage element to write data received from an input data stream and a plurality of read pointers, each configured to indicate a particular data location to read data from to generate a number of output data streams. The input data stream and the output data streams may be part of a data communications device.

Abstract: A method of forming edge metal lines to interconnect features in a semiconductor device. One embodiment comprises the steps of: patterning a first insulating layer to form a first feature having a first sidewall; depositing a metal layer over the first feature; and etching the metal layer so that a first edge metal line is formed adjacent to the first sidewall. The edge metal line may be substantially anisotropically etched to form the edge metal line. The edge metal line may comprise a plurality of metal layers. The edge metal line may also interconnect features in a semiconductor device (e.g., contacts). The method may further comprise the step of forming a protective coating over a portion of the metal layer such that the etching step may form a metal interconnect line and the edge metal line from the same metal layer. The metal interconnect line may comprise a bus that may have more current carrying capacity than the edge metal line.

Abstract: A method of reducing impurities in films to be deposited within a chemical vapor deposition (CVD) device includes steps of cleaning the process chamber of the CVD device, and depositing, prior to wafer processing, a gettering layer of, for example, phosphorous containing glass on interior surfaces of the process chamber. The gettering layer getters mobile alkali ions and substantially reduces or prevents outdiffusion of alkali ions and other impurities. The phosphorous containing glass may also be doped with boron. A blocking layer, such as undoped silicate glass, silicon nitride, silicon oxynitride or the like may be deposited on the gettering layer to trap impurities and to prevent phosphorous contamination in a applications sensitive to such contamination.

Abstract: A circuit comprising a sense amplifier, an evaluation circuit, a control circuit and a register circuit. The sense amplifier circuit may be configured to present a first output and a second output in response to (i) an input signal and (ii) an enable signal. The evaluation circuit may be configured to present an evaluation signal in response to the first and second outputs. The control circuit may be configured to present (i) a first clock signal, a second clock signal and an enable signal in response to (i) the evaluation signal and (ii) a wordline signal. The register circuit may be configured to hold either the first or second output in response to the first and second clock signals. The register circuit may be implemented as a master-slave register that may respond to the first and second clock signals.

Abstract: A single pump circuit for generating a variable high voltage that responds to more than one discrete input. The present invention uses a common pump circuitry to process a number of voltage inputs. Each of the voltage inputs can be a different input voltage and will be stepped up to a higher output voltage according to the design constraints of the pump circuitry. Since the pump circuitry is used for each of the inputs, without redundancy, the amount of chip real estate consumed is minimized. A switching system is implemented that detects which input has a voltage present and activates a particular path to the pump output accordingly.

Abstract: The present invention concerns a circuit and method to automatically test and disable defective rows in a FIFO or other buffer where the wordlines or rows of the FIFO buffer are driven by a shift register scheme. Additional enabled rows may be placed within the normal memory array. The additional enabled rows are substituted, as needed, for one or more defective rows. As a result, a defective row can be automatically disabled without effecting the operation of the FIFO, particularly the read or write data path. In one example, the disabling effect is achieved by using a comparison circuit to determine if the words read from the memory are accurate. The present invention can be used to effectively bypass any single shift register element or a multiple number of shift register elements.

Abstract: The present invention relates to a method of manufacturing an opening through a dielectric layer. The method comprises treating a polished dielectric layer with a wet etch selectively enchancing composition, such as buffered HF, prior to the formation of a patterned photoresist to improve the lateral-to-vertical wet etch ratio.

Abstract: A first circuit configured to present a first indication signal in response to a predetermined level of an input voltage and a second circuit configured to enter a suspend mode in response to the first indication signal. In one example, the second circuit may enter an active mode in response to a second indication signal received from an external device. In another example, the second circuit may be implemented as a microcontroller.

Abstract: A semiconductor structure that includes a silicon substrate which has a top surface, a diffusion region formed in the substrate adjacent to the top surface, a polysilicon gate formed on the top surface of the substrate adjacent to but not contacting the diffusion region, an insulator layer substantially covers the polysilicon gate and the diffusion region, the layer contains a via opening therein, and an electrically conducting plug filling at least partially the via opening providing electrical communication between the polysilicon gate and the diffusion region.