Abstract: A semiconductor structure that includes a silicon substrate which has a top surface, a diffusion region formed in the substrate adjacent to the top surface, a polysilicon gate formed on the top surface of the substrate adjacent to but not contacting the diffusion region, an insulator layer substantially covers the polysilicon gate and the diffusion region, the layer contains a via opening therein, and an electrically conducting plug filling at least partially the via opening providing electrical communication between the polysilicon gate and the diffusion region.

Abstract: A programmable logic device includes a plurality of clusters of logic elements. Each of the clusters may include a respective programmable interconnect matrix with each of the logic blocks of each cluster being coupled to the respective programmable interconnect matrix of the cluster. Each of the clusters may be symmetrically coupled to a row and a column of a global routing matrix. The row and the column of the global routing matrix may themselves be symmetrical and each row and/or column may be coupled to an input/output cell of the programmable logic device. The global routing matrix may comprise a plurality of programmable interconnections.

Abstract: A write control circuit for a semiconductor memory device includes a conventional write path responsive to a control input (e.g., an external write enable signal) to control the beginning of a write operation for a write driver, whilst a separate dedicated write disable path, responsive to the same control input, controls the end of the write operation for the write driver. The invention separates the end of write from the beginning of write by introducing a fast dedicated path designed primarily for ending the write. This dedicated path contains dedicated logic to generate an end of write signal at the disabling edge of the control input to disable the write driver quickly before a new memory cell is selected.

Abstract: A memory array comprising a plurality of storage elements and a logic circuit. The memory array may be configured to (i) receive a plurality of input data streams, (ii) store each of the plurality of input data streams in one or more of the storage elements in response to a plurality of control signals and (iii) present a plurality of output data streams in response to the plurality of input data streams. The logic circuit may present the plurality of control signals in response to the fullness of each of the plurality of storage elements.

Abstract: The present invention provides an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.

Abstract: A counter-bias scheme to reduce or eliminate charge gain in a single-poly or double-poly electrically erasable (E.sup.2) cell having separate program and read transistors which may be configured as a 6-wire cell includes applying a counter-bias voltage to the drain of a program select transistor of the E.sup.2 cell during a read operation. The counter-bias voltage may be approximately equal to a voltage on the floating gate of the cell during the read operation. The present scheme reduces the threshold voltage shifts which may otherwise be experienced in the cell during continuous read operations. In particular, the counter-bias voltage acts to reduce the electric field across the tunnel oxide of the program select transistor, thus reducing the charge gain on the floating gate.

Abstract: A circuit and method for framing an input data stream to a periodic signal. The circuit comprises a register circuit, a logic circuit and a multiplexor circuit. The register circuit may be configured to store information and to present a first and second output in response to (i) the input data stream and (ii) the periodic signal. The logic circuit may be configured to (i) detect a predetermined bit sequence and (ii) present a control signal in response to the information stored in the register circuit. The multiplexor circuit may be configured to present one or more multiplexed signals comprising the first and second outputs of the register circuit in response to the control signal.

Abstract: The present invention provides a circuit and method for manipulating the least significant bit (LSB) of the read and write count signal to generate a glitch free mutually non-exclusive decoder output. The present invention can be used to generate a logic to eliminate glitches in the inputs to a full/empty flag generator, an almost full/almost empty flag generator or a half-full/half-empty flag generator. The circuit can be extended to generate the logic to eliminate glitches in either direction as the count signals move across a boundary change in a half-full flag generation circuit.

Abstract: A circuit configured to generate an error signal that may be used to disable a loading mechanism (such as a loading mechanism in a wafer sorter). The circuit comprises a wafer sense circuit configured to generate a first pulse in response to a wafer passing a detection point, a pulse generator circuit configured to generate (i) a second pulse in response to a transition (e.g., a positive transition) of the first pulse and (ii) a third pulse in response to a transition (e.g., a negative transition) of the first pulse. An error detection block may be configured to generate an error signal in response to (i) the first pulse, (ii) the second pulse and (iii) the third pulse.

Abstract: A circuit including a register coupled to a control circuit. The register has a synchronous mode of operation and an asynchronous mode of operation. The a control circuit controls whether the register operates in the synchronous mode or the asynchronous mode. The circuit may further include a scan register having scan data. The control circuit may cause the register to operate in the synchronous or asynchronous mode in response to the scan data.

Abstract: An electrostatic discharge (ESD) protection circuit for an output transistor coupled to an I/O pin of an integrated circuit, including a logic circuit having at least one data input, a tristate enable input, and an tristate output coupled to a gate node of the output transistor wherein the tristate output is placed in a high impedance state in response to the tristate enable input. The ESD protection circuit also includes a tristate enable circuit which drives the tristate enable input according to the presence or absence of an ESD event on the I/O pin. During normal operation, the tristate enable circuit applies a first logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a low impedance state, and during an ESD event on the I/O pin, the tristate enable circuit applies a second logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a high impedance state.

Abstract: The output (3) of a level shifter (1) is split into two paths (4,5) with a delay (.tau..sub.1, .tau..sub.2) being introduced into at least one path to enable rise delay and fall delay to be controlled independently of one another. In the context of an integrated circuit which includes a memory device, the use of an additional path allows control of the set-up and hold times in that one transition can be speeded up or slowed down independently of the other transition to achieve the best possible set-up and hold times.

Abstract: A circuit comprising a plurality of phase locked loop circuits, a control circuit and a plurality of storage elements. Each of the plurality of phase locked loop circuits may present a recovered data signal and a recovered clock signal in response to one of a plurality of serial data streams, a clock signal and one of a plurality of indication signals. The control circuit may present a counter signal in response to the recovered clock signals. The plurality of storage elements may each be configured to present one of the indication signals in response to the clock signal, a select signal and the counter signal.

Abstract: A data mover which provides guaranteed transfer of data between two locations. The data mover includes a pair of data packet memories for input, a pair of data packet memories for output, and a controller which alternately switches each of the paired data packet memories between a data loading mode and a data unloading mode. The controller enables one of the paired data packet memories in the data loading mode and enables the other one of the paired data packet memories in the data unloading mode. The controller switches the modes of the paired data packet memories upon receiving an acknowledgement of moved data.

Abstract: The invention relates to a three-state content addressable memory cell with a comparison element operationally connected to the match line output that outputs a signal having (i) a first logic state in response to two inputs having different logic states and (ii) a second logic state in response to two inputs having the same logic states, a first data storage (element) having an input operationally connected to a first data input line and an output operationally connected to said comparison element, a second data storage element having an input operationally connected to a second data input line and an output operationally connected to an input to said comparison element, said content addressable memory cell storing a masked state by storing the same logic state on said first and said second storage elements, said match line output having no direct connection to said first and second data storage elements thereby providing operational isolation between said match line output and said storage elements.

Abstract: A semiconductor device (e.g., a zero-delay buffer) is provided which is capable of reducing current or power consumption without the use of a dedicated pin. The device may include a frequency detector that receives a detector input signal corresponding to or derived from a device input signal. The device input signal performs a first function during normal operation of the device. The detector determines whether the frequency of the detector input signal is less than a predetermined minimum, and if so, generates a power down signal configured to direct the device to reduce current or power consumption in at least one of its component circuits. The frequency detector may include a "one-shot" circuit responsive to the detector input signal for generating a frequency indicator signal, and a "power down" signal output circuit responsive to the frequency indicator signal for generating the power down signal.

Abstract: The present invention concerns a circuit comprising a memory array having a plurality of wordlines and a plurality of bitlines, a reference circuit, a column select circuit, an enable control circuit, and one or more sense amplifiers. The reference circuit may be configured to present a reference voltage signal in response to (i) a dummy wordline and (ii) a virtual ground signal, where the dummy wordline may be synchronized with each of the plurality of wordlines. The column select circuit may be configured to present the virtual ground signal in response to a column select signal. The enable control circuit may be configured to present an enable signal in response to the dummy wordline. The sense amplifiers may be configured to generate an output in response to (i) the enable signal, (ii) the reference signal and (iii) the bitlines.

Abstract: A mask-programmable and mask-programmed interconnect matrix is disclosed in which at least one of a plurality of output conductors may be interconnected via a mask-programmed interconnection to at least one input conductor. Also disclosed is a method of creating a mask programmed device implementing a logic function comprising the steps of creating a field-programmable device or array and a mask-programmable device or array, determining an interconnect map that would implement the logic function on the field programmable device or array, and implementing the interconnect map on the mask programmable device or array by mask programming the interconnects determined in the interconnect map onto the mask programmable device or array.

Abstract: A combinational logic feedback circuit ensures correct power-on-reset of a 4-bit synchronous shift register used to generate a plurality of page select signals. The combinational circuit monitors the plurality of page select signals and asserts an invalidity signal when an invalid state is detected. A deglitch circuit inhibits or suppresses glitches which may be output from the combinational circuit due to state transitions of one or more of the page select signals. The deglitch circuit generates in response thereto a reset signal which is applied to the synchronous shift register to reset the shift register to output a valid state.

Abstract: A mechanism for determining a CPU's core-to-bus frequency ratio in a computer system using the CPU itself, rather than an external agent, to sample the external pins on RESET and latch their core/bus frequency ratio information into an internal register. By accessing the information in this internal register, it is possible for the BIOS or any other software to read the internal to external clock ratios and optimize the performance of the system.