Abstract: A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.

Abstract: The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size.

Abstract: A novel synchronous latching scheme is disclosed for use in connection with an EPROM device having a limited number of pins for control signals. A negative edge-triggered d-type master-slave latch having a D-input, and a clock input is provided for generating a program/verify read mode signal. The D-input is coupled to a V.sub.pp /OE control terminal of the EPROM, while the clock input is coupled to a CE/PGM control terminal. During a program interval, while an enabled memory cell is being programmed, and the V.sub.pp control terminal is at a supervoltage, the latch is operable to capture the high level on such control terminal, and provide the high level as an output to define a verify read mode signal. During an immediately-following program verify read interval, the asserted verify mode signal is used to adjust the sense amplifier of the EPROM device so as to provide an increased read margin. During such verify program interval, the V.sub.

Abstract: The invention can be used to monitor the cleaning effectiveness of a cleaning system in which vibrations (such as, for example, vibrations having a megasonic or ultrasonic frequency) are applied to a volume of fluid (e.g., water) in which an object to be cleaned (e.g., a substrate, such as semiconductor wafer or other semiconductor substrate) is at least partially immersed. Generally, the invention monitors the state of a physical characteristic of the fluid during the application of the vibrations, thus providing a more direct and accurate measure of the effectiveness of the cleaning than has heretofore been obtainable. For example, the magnitude of the acceleration of a pressure wave produced in the volume of fluid by the vibrations can be monitored, thus enabling the amplitude and/or frequency of the pressure wave to be determined.

Abstract: A circuit for generating a pulse signal in response to an input signal. The circuit provides a pulse width for the pulse signal. A first logic device receives the input signal and generates a first intermediate signal. A delay device is coupled to the first logic device and receives the first intermediate signal. The delay device generates a second intermediate signal in response to the first intermediate signal after a period of time. The second intermediate signal has the same state as the second intermediate signal. A second logic device is coupled to both the first logic device and the delay device. The second logic device generates the pulse signal in response to the first intermediate signal.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a plurality of input signals. Circuitry for synchronizing the asynchronous logic derived clock signal to a reference clock signal is coupled to the circuitry for generating. The circuitry for synchronizing generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal is produced only when the input signals from which the asynchronous logic derived clock signal is created are recognized as proper input signals and the synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input signals. Spurious input signals or noise are rejected.

Abstract: A circuit for distributing data from a common input source to a number of individual memory cells in a memory array. A multi-bit counter is used to distribute a timing signal to a number of decoder blocks. Each of the decoder blocks receives both a data input signal and the timing signal at all times. When a particular timing signal is present at a given decoder, the input signal containing a fixed width data word is passed through to the corresponding memory array for storing the data word. The present invention reduces the number of internal signal lines necessary to implement the control function and significantly reduces the chip area needed to generate the signal lines.

Abstract: A novel waveform generating for generating a waveform having symmetrical rise and fall times. The waveform generator of the present invention includes a first current source, a second current source, a MOS capacitor and a clamping circuit. The first current source and the second current source are coupled to a node such that current generated by the first current source flows into the capacitor and current generated by the second current source flows out of the capacitor. The clamping circuit is also coupled to the node such that the output voltage generated by the waveform generator is limited to a minimum and a maximum value. Therefore, by controlling the current flowing into the node, and the capacitance at the node, the rate at which the output voltage changes over time is controlled. As such, a waveform having very precise rise and fall times is generated.

Abstract: The present invention concerns a mask-programmed cell comprising an input, an output and a transistor. The transistor has a first terminal and a second terminal. The cell may be configured in a first of three possible states when (a) the cell input is coupled to the first terminal via a first of two mask-programmed interconnects, and (b) the second terminal is coupled to the output. The cell may be configured in a second of three possible states when (a) a complement of the cell input is coupled to the first terminal via a second of the two mask-programmed interconnects, and (b) the second terminal is coupled to the output. The cell may be configured in a third of the three possible states when either the second terminal or the output is coupled to a predetermined level signal.

Abstract: Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w.sub.mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w.sub.mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors.

Abstract: A programmable device includes a circuit for generating an asynchronous logic derived clock signal derived from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating the asynchronous logic derived clock signal. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous clock signal and a reference clock signal. The programmable device further includes a circuit for suspending a clock signal. In one embodiment, a logic derived clock signal is generated and synchronized with a synchronous clock signal. In synchronizing the logic derived clock signal an intermediate signal is generated during a first clock cycle of the synchronous clock signal and is combined with the synchronized logic derived clock signal during a second clock cycle of the synchronous clock signal to produce a suspendable clock signal.

Abstract: A programmable device includes means for generating an asynchronous logic derived clock signal from one or more of a plurality input signals. Means for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the means for generating the asynchronous logic derived clock signal. The means for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal.

Abstract: A memory device including a first block of random access memory (RAM) cells having preprogrammed states, a second block of random access memory cells, and a select circuit configured to reset the first block of RAM cells to their preprogrammed states. When the first block of memory cells are reset to their preprogrammed states, the first block of memory cells may function as ROM memory cells that may be accessed at RAM speeds. The first block of RAM cells may not require additional nonvolatile circuitry in order to perform the ROM function; rather, the first block of RAM cells may each be configured to operate as both a volatile and nonvolatile memory cell using the same cell structure. For one embodiment, the select circuit alters the power applied to the first block of RAM cells to cause these RAM cells to perform a ROM function.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to be a reference clock signal are coupled to the circuitry for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal but only when the input signals are recognized as clocking signals. That is, the synchronizing circuits discriminate between valid input signals and spurious signals or noise.

Abstract: The present invention concerns an output buffer, which overcomes previous disadvantages of driving transmission line loads by providing a variable output impedance in response to the load on the output. The buffer generally comprises a pullup device for providing a high voltage at the output in response to a first input, a pulldown device configured to provide a low voltage at the output in response to a second input and a second pulldown device configured to provide additional low drive at the output. The second pulldown device provides an impedance at the output which varies with respect to the voltage present at the output.

Abstract: A programmable I/O cell with a multiplicity of configurations and data conversion options implemented through the use of antifuses. Increased logic utilization and reduced number of components necessary to implement such designs by using the registers in the I/O cell to implement data conversion functions thereby saving the logic and registers of the FPGA logic cells for implementation of other functions is achieved. Serial-to-parallel and parallel-to-serial data conversion operations utilize adjacent registers in adjacent cells to perform shift operations.

Abstract: A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a plurality of input signals. Further circuitry for synchronizing the asynchronous logic derived clock signal to a reference clock signal is coupled to the generating circuitry. The synchronizing circuit generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal is produced only when the input signals from which the asynchronous logic derived clock signal is created are recognized as proper input signals and the synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input signals. Spurious input signals or noise are rejected.

Abstract: The invention relates to a mixed voltage bus system and in particular, interfaces between a number of integrated circuits and a bus where some of the integrated circuits operate at one logic level and others operate at a different logic level. An overvoltage tolerant interface for a semiconductor integrated device particulary useful in such a system may contain a pad, a pull-up transistor coupled to the pad, a voltage supply having an operating voltage, and an isolation switch operative to isolate the pull-up transistor from the voltage supply when a voltage at the pad exceeds the operating voltage of the voltage supply.

Abstract: A process for polishing a layer on a semiconductor wafer in which the incidence of undesirable scratches on the polished surface is reduced by using a multiple step polishing procedure. A relatively hard polishing pad is used first to planarize the wafer surface, using a chemically reactive and abrasive slurry. A second polishing step is then carried out on a relatively soft polishing pad, using a slurry to remove or reduce scratches introduced by polishing with the hard pad. A final polishing step is performed on the soft polishing pad using de-ionized water to remove particles from the surface of the wafer.

Abstract: A memory cell includes non-volatile and volatile storage elements and is configured to dynamically alter threshold voltages of the non-volatile storage elements to store states of the volatile storage elements. The volatile storage elements may be stacked gate PMOS transistors, one of which may include a gate structure having a poly-silicon control gate disposed over a poly-silicon floating gate. The control gate and floating gate may be separated by a coupling dielectric, which may be an ONO stack or a deposited oxide. The gate structure may be disposed over an active area of a substrate including a drain and a source of the PMOS transistor. The active area may be disposed in an n-well of the substrate. A first of the volatile storage elements may comprise an NMOS transistor which is formed in a p-well of the substrate. The p-well may further be disposed in an n-well.