Abstract: A memory device in which a circuit reads a cell condition. A terminal provides voltage to a bit line of the circuit via a switch. The circuit outputs and enables storage of a first logical value when the voltage provided from the terminal does not exceed a threshold value. The circuit outputs and enables storage of a second logical value when the voltage provided from the terminal exceeds the threshold value. The output and storage occurs in the absence of an electrical connection between the cell and circuit. The switch provides voltage supplied from the terminal to the bit line of the circuit. The voltage increases from a value which does not exceed the threshold to a value which exceeds the threshold.

Abstract: A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly or non-doped material will become crystalline (?30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack.

Abstract: A semiconductor device includes a first wiring hoard, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.

Abstract: A memory mat (101) includes a main body portion (200) that includes a first capacitor (203A), a linear conductive film (204) that is formed between the main body portion (200) and a peripheral circuit (104), and a second capacitor (203B) that is formed to be in contact with the conductive film (204) at a bottom of the second capacitor (203B). The first capacitor (203A) is in contact with a contact layer (202) at a bottom of the first capacitor (203A).

Abstract: To provide a semiconductor device including a capacitor which includes a cylindrical or columnar lower electrode, a support film in contact with the upper portion of the lower electrode for supporting the lower electrode, a dielectric film covering the lower electrode and the support film, and an upper electrode facing the lower electrode with the dielectric film interposed therebetween, wherein the dielectric film has a first thickness on the upper surface of the support film and a second thickness thinner than the first thickness on the side surface of the lower electrode, and thereby the mechanical strength of the support film is increased.

Abstract: Disclosed herein is a device that includes: first lines formed on a first wiring layer extending in a first direction; second lines formed on a second wiring layer extending in a second direction; and conductor plugs connecting the first lines to the second lines such that the first and second lines form a mesh-structure wiring. The first lines include first enlarged portions at intersection positions where the first and second lines cross to each other, a width in the second direction of the first enlarged portions is wider than a line width of the first lines at other than the intersection position. The second lines include second enlarged portions at the intersection positions, a width in the first direction of the second enlarged portions is wider than a line width of the second lines at other than the intersection position.

Abstract: In a vertical MOS transistor in which a semiconductor pillar is formed by etching a semiconductor substrate in a portion surrounded by an isolation film, the semiconductor pillar is covered with a gate insulating film and a gate electrode to be made a channel part, and diffusion layers to be a source and a drain are included on a top and a bottom of the channel part, electrode which controls potential of a gate electrode material is formed in gate electrode material formed on a side surface of isolation film, in order to eliminate a parasitic MOS operation by the gate electrode material remaining on the side surface of the isolation film.

Abstract: When overdriving a first power supply voltage supplied to a sense amplifier, a line for the first power supply voltage and a line for a second power supply voltage which is higher than the first power supply voltage are connected to each other by a first transistor, thereby boosting the first power supply voltage. When the first power supply voltage drops upon activation of the sense amplifier, the line for the first power supply voltage and the line for the second power supply voltage are connected to each other by a second transistor, thereby increasing the current supply capability. The first transistor and the second transistor are fully driven to operate as switches.

Abstract: Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that includes a slot, a large number of external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The arrangement includes a first bonding finger array, which is located at a close distance from each longer side of the slot, and a second array, which is located at a farther distance than the distance of the first bonding finger array from each longer side of the slot. The central section of the bonding finger area includes the second bonding finger array, and the end sections of the bonding finger area include the first bonding finger array.

Abstract: A semiconductor device includes a first pad, and a sub-trunk line elongated in a first direction; a main-trunk line arranged between the first pad and the sub-trunk line and elongated in the first direction. The semiconductor device further includes a first plug line elongated in a second direction crossing the first direction, the first plug line being connected between the first pad and the main-trunk line without being direct contact with the sub-trunk line. The semiconductor device further includes a second plug line elongated in the second direction, the second plug line being connected between the main-trunk line and the sub-trunk line, and a first element coupled to the sub-trunk line.

Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 ??cm. Advantageously, the electrode layers are conductive molybdenum oxide.

Abstract: Disclosed herein is a device that includes: a data terminal; an output buffer coupled to the data terminal, the output buffer including a first output unit having a plurality of first output transistors of a first conductivity type and a second output unit having a plurality of second output transistors of a second conductivity type; and a calibration circuit including a first code generation unit that generates a first control code that controls an impedance of the first output unit by performing a first calibration operation based on an impedance of a first reference unit and a second code generation unit that generates a second control code that controls an impedance of the second output unit by performing a second calibration operation based on an impedance of a second reference unit. The calibration circuit performs the first and second calibration operations in parallel.

Abstract: Disclosed herein is a device that includes: a data terminal; a plurality of memory banks; and a control circuit configured to control a data transfer between the data terminal and the memory banks. The control circuit is configured to set a read latency in response to a burst length.

Abstract: A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V2 from a first voltage V1; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current control signal OVDR. The control circuit includes a slew-rate processing unit that makes a second slew rate of the current control signal OVDR related to the second transition be smaller than a first slew rate of the current control signal OVDR related to the first transition.

Abstract: A semiconductor device includes: a clock generator generating a first internal clock signal based on an external clock signal; a clock divider generating second and third internal clock signals based on the first internal clock signal and including an edge adjustor adjusting a timing of one of rising and falling edges of the third internal clock signal, an adjustment information holder supplying an edge adjustment signal to the edge adjustor, and a data strobe generator receiving the second and third internal clock signals to generate a first data strobe signal based on the second internal clock signal, and a second data strobe signal with a phase different from that of the first data strobe signal, based on the third internal clock signal. The edge adjustor adjusts the timing of at least one of the rising and falling edges of the third internal clock signal based on the edge adjustment signal.

Abstract: In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequentially with the precursor pulse with a purge step used to remove the non-adsorbed EDC from the process chamber before the precursor is introduced. In some embodiments, the EDC pulse is introduced using a vapor draw technique or a bubbler technique. In some embodiments, the EDC pulse is introduced in the same gas distribution manifold as the precursor pulse. In some embodiments, the EDC pulse is introduced in a separate gas distribution manifold from the precursor pulse.

Abstract: A semiconductor memory device includes a plurality of word lines wired in a first direction, a plurality of bit lines wired in a direction crossing the first direction, a memory cell array including a plurality of DRAM cells provided corresponding to intersections between the word lines and the bit lines, a word line driver which drives the word lines, and a plurality of word line potential stabilization transistors connected to the respective word lines and disposed on an opposite side of the word line driver with the memory cell array sandwiched between the word line potential stabilization transistors and the word line driver, each word line potential stabilization transistor turning on when the word line adjacent to a relevant one of the word lines is selected, thereby connecting the relevant word line to a non-selected potential, and turning off when the relevant word line is selected.

Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate having a device isolation groove defining first to fourth device formation portions. The second device formation portion is separated from the first device formation portion. The third device formation portion extends from the first device formation portion. The third device formation portion is separated from the second device formation portion. The fourth device formation portion extends from the second device formation portion. The fourth device formation portion is separated from the first and third device formation portions. The third and fourth device formation portions are positioned between the first and second device formation portions.

Abstract: A semiconductor device includes a semiconductor substrate having a principal surface, a first conductor formed on the semiconductor substrate and including a conductive film having a first side wall portion and a first bottom surface portion both of which are continuously formed on a first trench having a first width in a direction parallel to the principal surface, and a second conductor formed on the semiconductor substrate and including a conductive film having a second side wall portion and a second bottom surface portion both of which are continuously formed on a second trench having a second width in a direction parallel to the principal surface, the second width being larger than the first width.

Abstract: Disclosed herein is a device that includes: a semiconductor substrate; a first semiconductor pillar having a side surface that is substantially perpendicular to a main surface of the semiconductor substrate; an insulator pillar having a side surface that is substantially perpendicular to the main surface of the semiconductor substrate and a top surface that is substantially parallel to the main surface of the semiconductor substrate; a first gate electrode covering the side surface of the first semiconductor pillar with intervention of a first gate insulation film; an extended gate electrode covering the side surface of the insulator pillar, the extended gate electrode being configured integrally with the first gate electrode; and a conductive film formed on the top surface of the insulator pillar, the conductive film being in contact with the extended gate electrode in a position above the top surface of the insulator pillar.