Patents Assigned to Elpida Memory, Inc.
  • Patent number: 8541316
    Abstract: In a method of forming a dense contact-hole pattern in a semiconductor device, the method uses a self-align double patterning technique including forming a square or triangular lattice dot pattern on double layers of mask materials, forming first holes in the upper mask material and second holes wider than the first holes in the lower mask material by double patterning, additionally forming an insulating layer to a thickness such that the first holes are closed such that voids are left in the second holes, and transferring the shape of the voids to a base layer.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: September 24, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 8542547
    Abstract: A semiconductor device comprises a first sense amplifier, first to third transmission lines, and first to third switches. The first and second transmission lines are connected to the first sense amplifier. The first and third switches control connections of the first to third transmission lines, and the second switch controls a connection between a fixed potential and third transmission line. When the second transmission line is not accessed, the first and third switches are brought into a non-conductive state and the second switch is brought into a conductive state, and the fixed potential is supplied to the third transmission line, thereby suppressing influence of the coupling noise between the transmission lines.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: September 24, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 8542546
    Abstract: A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122, and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The device also includes a test mode in which the data latch circuit latches data read to the data input/output terminals in a read operation and writes previously latched data in the memory cell array without newly latching data from the data input/output terminals in a write operation.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: September 24, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshinori Matsui, Shoji Kaneko
  • Patent number: 8542516
    Abstract: A device that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: September 24, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hideyuki Yoko
  • Patent number: 8541868
    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: September 24, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Hiroyuki Ode
  • Patent number: 8542523
    Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed over the first electrode film. A second electrode film is formed over the dielectric film. The second electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the second electrode film. The dopants and their distribution are chosen so that the crystal structure of the surface of the electrode is not degraded if the electrode is to be used as a templating structure for subsequent layer formation. Additionally, the dopants and their distribution are chosen so that the work function of the electrodes is not degraded.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: September 24, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Karthik Ramani, Wim Y. Deweerd, Hiroyuki Ode
  • Patent number: 8541283
    Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 24, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Mitsuhiro Horikawa, Kenichi Koyanagi, Hiroyuki Ode, Xiangxin Rui
  • Patent number: 8542544
    Abstract: A semiconductor device may include, but is not limited to, first and second memory regions, and first to fifth control circuits. The first and second memory regions are mutually exclusive at the same time. The first control circuit performs a first access to the first memory region. The second control circuit performs a second access to the second memory region. The third control circuit controls activation and deactivation of the first and second control circuits based on a first logic received from a plurality of first external terminals. The fourth control circuit switches between the first and second accesses based on at least a second logic received from a second external terminal. The fifth control circuit controls validation and invalidation of the fourth control circuit.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: September 24, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Katsuyoshi Komatsu, Koji Mine
  • Publication number: 20130242671
    Abstract: Disclosed herein is a device that includes an amplifier, a first transistor coupled between the first power supply line and the internal node and including a gate terminal supplied with a bias voltage, a second transistor coupled between the internal node and the second power supply line and including a gate terminal coupled to the output terminal of the amplifier, a third transistor coupled between the first power supply line and the output node and including a gate terminal coupled to the internal node, a divider configured to produce a first discharge path from the output node to the second power supply line to establish the feedback voltage to the amplifier, and a first switch circuit supplied with a first signal and coupled between the output node and the internal node.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 19, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Chiara Missiroli
  • Publication number: 20130240966
    Abstract: A semiconductor device includes a semiconductor body including a first upper surface with a first side surface extending downwardly therefrom, a second upper surface with a second side surface extending downwardly therefrom, and a bottom surface interfacing first and second side surfaces. The first and second side surfaces and the bottom surface together define a groove. A conductive film partially fills the groove with an intervention of an insulating film therebetween so the conductive film terminates at a first intermediate portion of the first side surface between the first upper surface and the bottom surface and at a second intermediate portion of the second side surface between the second upper surface and the bottom surface. A distance between the first intermediate portion of the first side surface and the first upper surface exceeds a distance between the second intermediate portion of the second side surface and the second upper surface.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 19, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Koji HAMADA
  • Patent number: 8537635
    Abstract: A semiconductor device comprises a floating body type transistor and first and second circuits. The transistor has a floating body and a source-drain path inserted between first and second circuit nodes. The first circuit supplies a first signal to the gate of the transistor, and the first signal changes between a first logic level that holds the transistor in a non-conductive state and a second logic level that directs the transistor into a conductive state. The second circuit supplies a first voltage level near the second logic level to the first circuit node and supplies a second voltage level near the second logic level to the second circuit node, each as a level in a state where the transistor is not utilized. Thereby the gate capacitance of the transistor can be kept small as viewed from the gate, and high-speed operation and a reduction in consumption current can be achieved.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: September 17, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Soichiro Yoshida
  • Patent number: 8536711
    Abstract: A semiconductor device includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a first silicon film in contact with an inner surface of the isolation trench, a second silicon film in contact with an outer surface of the isolation trench, and an insulation film provided between the first and second silicon films.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: September 17, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Shiro Uchiyama
  • Patent number: 8536642
    Abstract: A vertical transistor comprises a semiconductor region, a pillar region formed on the semiconductor region, a gate insulating film formed so as to cover a side surface of the pillar region, a gate electrode formed on the gate insulating film, a first impurity diffusion region formed in an upper portion of the pillar region, and a second impurity diffusion region formed in the semiconductor region so as to surround the pillar region. The first impurity diffusion region is formed so as to be spaced from the side surface of the pillar region.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: September 17, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kazuo Ogawa
  • Patent number: 8537626
    Abstract: A semiconductor device includes a data input/output circuit connected to the memory cell array via a sense circuit, and an access control circuit that controls access to the memory cell array. The access control circuit includes: a first signal unit outputting a first signal for activating or inactivating a word line; a second signal unit outputting a second signal for activating or inactivating a bit line and the sense circuit; a third signal unit outputting a third signal for starting or stopping a supply of an overdrive voltage to the sense circuit; and a fourth signal unit outputting a fourth signal for inactivating the word line. The period during which the third signal remains activated is determined in accordance with the magnitude of an external voltage. In the fourth signal unit, the timing to generate the fourth signal is determined independently of the magnitude of the external voltage.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: September 17, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroki Fujisawa, Kazuhisa Ureshino
  • Patent number: 8539410
    Abstract: A method includes preparing a chip-stack structure in which a first memory chip is stacked over a first main surface of a second memory chip, data electrodes of the first and second memory chips being electrically connected and a data signal outputted from the data electrode of the first memory chip being conveyed on a side of the second main surface of the second memory chip, accessing the first memory chip so that the data signal is outputted from the first memory chip and appears on the side of the second main surface of the second memory chip in first access time, accessing the second memory chip so that a data signal is outputted and appears on the side of the second main surface of the second memory chip in second access time, and setting output timing adjustment information into at least one of the first and second memory chips.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: September 17, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Naohisa Nishioka, Chikara Kondo
  • Publication number: 20130235669
    Abstract: Disclosed herein is a device that includes a first transistor coupled between an input terminal and an output terminal and including a control gate, a voltage-generating circuit configured to produce a voltage at the control gate of the first transistor, and a discharge circuit coupled between the input terminal of the first transistor and the control gate of the first transistor, the discharge circuit responding to a discharge signal to perform a discharge operation such that an electrical charge is discharged from the output terminal to the input terminal of the first transistor.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Nicola Maglione, Osama Khouri, Stefano Sivero
  • Publication number: 20130234342
    Abstract: A semiconductor device includes a first semiconductor chip including a plurality of driver circuits and an output switching circuit coupled to the plurality of driver circuits. The device also includes a second semiconductor chip and a plurality of through silicon vias provided on at least one of the first and second semiconductor chips. The output switching circuit is coupled between the plurality of driver circuits and the plurality of the through silicon vias, and outputs each of signals from the plurality of driver circuits to corresponding one of the plurality of through silicon vias.
    Type: Application
    Filed: April 29, 2013
    Publication date: September 12, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Kayoko Shibata, Hitoshi Miwa, Yoshihiko Inoue
  • Patent number: 8530311
    Abstract: Disclosed herein is a method of manufacturing a semiconductor device. The method comprises forming a first silicon film on a semiconductor substrate, forming a second silicon film on the first silicon film, forming a third silicon film on the second silicon film, and forming a first diffusion barrier film on the third silicon film. The method further comprises performing a thermal treatment to diffuse an impurity included in the second silicon film into at least the first silicon film and the semiconductor substrate, respectively.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: September 10, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Takayuki Matsui
  • Patent number: 8530348
    Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: September 10, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Edward L. Haywood, Hiroyuki Ode, Gerald Richardson
  • Patent number: 8531010
    Abstract: A semiconductor structure may include, but is not limited to: a semiconductor substrate; a first semiconductor structure extending upwardly over the semiconductor substrate; and a second semiconductor structure extending upwardly over the semiconductor substrate, the first and second semiconductor structures being aligned in a first <100> direction.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: September 10, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Kiyonori Oyu, Kazuhiro Nojima