Patents Assigned to Elpida Memory, Inc.
  • SEMICONDUCTOR DEVICE
    Publication number: 20130313689
    Abstract: In a connecting portion between an interconnection and a first bump which is a part of a through electrode penetrating a semiconductor chip and which penetrates a semiconductor substrate, a protruding portion protruding from the interconnection to the side of the first bump is provided. The protruding portion may be made of an insulating material and may be made of a conductive material.
    Type: Application
    Filed: May 20, 2013
    Publication date: November 28, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Koji TORII, Nobuyuki NAKAMURA
  • SENSE AMPLIFIER CIRUIT AND SEMICONDUCTOR DEVICE
    Publication number: 20130315018
    Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.
    Type: Application
    Filed: November 13, 2012
    Publication date: November 28, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Kazuhiko Kajigaya, Soichiro YOSHIDA, Yasutoshi YAMADA
  • Semiconductor device and control method thereof
    Patent number: 8593895
    Abstract: Disclosed herein is a semiconductor device comprising an array having a hierarchical bit line structure, global bit lines adjacent to each other, local bit lines corresponding to the global bit lines, hierarchical switches, precharge circuits precharging the global bit lines, precharge circuits precharging the local bit lines, and a control circuit. When performing a test of the array, precharge voltages for the global bit lines are set to potentials different from each other, and the control circuit controls the potentials to be applied to the local bit lines through the global bit lines and the hierarchical switches.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: November 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Shinichi Takayama, Kazuhiko Kajigaya
  • Memory controller, semiconductor storage device, and memory system including the memory controller and the semiconductor storage device for outputting temperature value in low power consumption mode
    Patent number: 8593897
    Abstract: A memory system includes a clock generation circuit, a memory device, and a controller. The memory device includes output circuits and a temperature sensor, the output circuits configured to output data at an output timing obtained based on a clock signal supplied from the clock generation circuit. The controller includes input circuits that receive the data outputted from the memory device at an input timing obtained based on a clock signal supplied from the clock generation circuit and a correction value setting circuit that adjusts the input timing based on a temperature value from the temperature sensor.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: November 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Kunihiko Kato, Toru Ishikawa
  • Semiconductor device, information processing system including same, and controller for controlling semiconductor device
    Patent number: 8593899
    Abstract: To improve the access efficiency of a semiconductor memory that includes a plurality of memory chips. Based on a layer address, a bank address, and a row address received in synchronization with a row command, and a layer address, a bank address, and a column address received in synchronization with a column command, a memory cell selected by the row address and column address in a bank selected by the bank address included in a core chip selected by the chip address is accessed. This can increase the number of banks recognizable to a controller, thereby improving the memory access efficiency of the semiconductor device which includes the plurality of memory chips.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: November 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Akira Ide
  • Semiconductor memory device having fuse elements programmed by irradiation with laser beam
    Patent number: 8593894
    Abstract: A relief-address control unit of a semiconductor memory device includes a fuse storage unit and a relief circuit. The fuse storage unit includes a plurality of fuse elements that are made nonconductive by irradiation with a laser beam, and a protective film with an opening directly above the fuse elements to facilitate the laser beam to pass through. The relief circuit specifies a relieved address based on a nonconductive state of the fuse elements. The opening is in a unified form along a long-side direction of the fuse storage unit. Further, the relief circuit is arranged adjacent to a short-side end of the fuse storage unit.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: November 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Tetsuya Arai
  • Semiconductor device and test method thereof
    Patent number: 8593891
    Abstract: A semiconductor device includes a plurality of core chips to which chip identification information different from each other is allocated and an interface chip are layered, the plurality of core chips are commonly connected to the interface chip through a first current path including at least a through silicon via, the interface chip serially supplies an enable signal to the plurality of core chips through the first current path, and the plurality of core chips are activated based on a logic level of a bit corresponding to the chip identification information among a plurality of bits configuring the enable signal. The present invention can reduce the number of through silicon vias required to supply an enable signal.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: November 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Naohisa Nishioka
  • Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device
    Patent number: 8593893
    Abstract: A controller includes a set of first terminals to be coupled to a device that is under control of the controller, and a control circuit configured to generate and output onto the set of first terminals edge specifying information that takes a selected one of first and second states, the edge specifying information being supplied to the device to cause the device to activate a data strobe signal at a first timing when the selected one of the edge specifying information is the first state and at a second timing, that is different from the first timing, when the edge specifying information is the second state, the control circuit being further configured to generate and output onto the set of first terminals a read command, the read command being supplied to the device to cause the device to return to the controller a data signal.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 26, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Atsuo Koshizuka
  • DIFFERENTIAL AMPLIFIER CIRCUIT HAVING PLURAL CURRENT MIRROR CIRCUITS
    Publication number: 20130307622
    Abstract: Disclosed herein is a differential amplifier circuit that includes: first and second transistors coupled to form a differential circuit; a first current mirror circuit generating first and second currents in response to a third current flowing through the first transistor; and a second current mirror circuit generating a fourth current in response to a fifth input current. A sum of the second and fourth currents flowing through the second transistor.
    Type: Application
    Filed: May 10, 2013
    Publication date: November 21, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hitoshi TANAKA
  • SEMICONDUCTOR DEVICE
    Publication number: 20130307056
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate including first, second and third surfaces, the second surface being placed above the first surface, the third surface having first and second edges connecting to the first and second surfaces, respectively; an isolation region including an insulator and formed on the first and third surfaces; an active region including the second surface and fenced with the insulator of the isolation region; and first and second semiconductor pillars each protruding upwardly from the second surface in the active region, wherein the first semiconductor pillar is thinner than the second semiconductor pillar.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 21, 2013
    Applicant: Elpida Memory, Inc
    Inventor: Yoshihiro TAKAISHI
  • SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER CIRCUIT
    Publication number: 20130308403
    Abstract: Disclosed herein is a device that includes: a first control element that controls an amount of current flowing between a second line and a first node according to a potential of a first line; a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line; a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential; a second control circuit that performs a second operation to connect the first node to the second node; and a third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation.
    Type: Application
    Filed: May 15, 2013
    Publication date: November 21, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Izumi NAKAI, Takeshi OHGAMI, Noriaki MOCHIDA, Yasuhiro MATSUMOTO
  • Stacked semiconductor chips having circuit element provided with each of the semiconductor chips
    Patent number: 8587117
    Abstract: A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: November 19, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Shinichi Takayama, Kazuo Ono, Tomonori Sekiguchi, Akira Kotabe, Yoshimitsu Yanagawa
  • Semiconductor memory device having selective activation circuit for selectively activating circuit areas
    Patent number: 8588023
    Abstract: A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included in a memory bank that is selected based on the bank selective signal, activates any one of the circuit areas based on the address signal, and deactivates at least one of rest of the circuit areas. According to the present invention, the power consumption can be reduced in an active state by a dynamic power control in response to an address signal, not by entire power control by an external command.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: November 19, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Makoto Kitayama
  • Method of forming dielectric film and capacitor manufacturing method using the same
    Patent number: 8586430
    Abstract: In a method of manufacturing a capacitor, a lower electrode of a capacitor is formed on or above a semiconductor substrate. An ozone gas and an inert gas are simultaneously introduced for a predetermined period into a reaction chamber of an atomic layer deposition apparatus in which the semiconductor substrate is set. Then, the ozone gas is exhausted from the reaction chamber by stopping the introduction of the ozone gas and introducing only the inert gas into the reaction chamber, after the introduction. A capacitive dielectric film is formed on the lower electrode by an atomic layer deposition (ALD) method in the atom layer deposition apparatus. An upper electrode of the capacitor is formed on the capacitive dielectric film after the capacitive dielectric film is formed.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: November 19, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kenji Komeda
  • Semiconductor device that suppresses malfunctions due to noise generated in internal circuit
    Patent number: 8587097
    Abstract: A semiconductor device includes a first pad row and a second pad row, a first ground potential supply electrode which is connected to a first interconnect provided near the first pad row, and a second ground potential supply electrode which is connected to a second interconnect provided near the second pad row. The first pad row includes a first pad connected to the first circuit within the chip and connected to the first interconnect via a first bonding wire, and includes a second pad connected to a second circuit within the chip and connected to the second interconnect via a second bonding wire crossing over the second pad row.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: November 19, 2013
    Assignee: Elpida Memory Inc.
    Inventors: Hiromasa Takeda, Satoshi Isa, Shotaro Kobayashi, Mitsuaki Katagiri
  • Semiconductor device having current change memory cell
    Patent number: 8588019
    Abstract: A semiconductor device comprises a first transistor connected between a bit line and a sense node, and a second transistor amplifying a signal of the sense node. A first potential applied to a gate of the first transistor, a second potential supplied to the sense node, and a third potential supplied to the bit line are controlled so that the first potential applied to a gate of the first transistor is between the second and third potentials, the second potential is set larger than the third potential, and a predetermined potential obtained by subtracting a threshold voltage of the first transistor from the first potential is smaller than the third potential and higher than a low potential supplied to the second transistor. A potential of the bit line transitions from the third potential toward the low potential in accordance with data of a current change memory cell.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: November 19, 2013
    Assignee: Elpida Memory Inc.
    Inventor: Kazuhiko Kajigaya
  • Device
    Patent number: 8587035
    Abstract: A device includes a semiconductor substrate, a first local bit line formed in the semiconductor substrate and elongated in a first direction, a first insulating layer on the semiconductor substrate, a first global bit line formed on the first insulating layer, a first path formed in the first insulating layer to couple a first end of the first local bit line with the first global bit line, and a second path formed in the first insulating layer to couple a second end of the first local bit line with the first global bit line.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: November 19, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Shinichi Takayama, Yasutoshi Yamada
  • Semiconductor device and method
    Patent number: 8588011
    Abstract: A semiconductor device is provided with first and second main word lines, and a control circuit. The control circuit, in response to a command signal received from outside of the semiconductor device, activates the first main word line at a first timing, and activates the second main word line at a second timing different from the first timing, the first main word line maintaining an activation state at said second timing.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: November 19, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Toshiyuki Sato
  • ROW DRIVER ARCHITECTURE
    Publication number: 20130301361
    Abstract: Devices and circuits for row driver in a memory device. The proposed row driver circuit architectures may reduce size of the row driver circuitry and enhance the row driver circuit's reliability. Specifically, the proposed embodiments of the row driver may reduce the required sizing of the boosting capacitor or alternatively eliminate the boosting capacitor entirely. Further, the embodiments of the row driver may reduce the risk of charge-leakage on K-nodes, enhancing the row driver's reliability in driving the x-path of the memory array.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 14, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Chiara Missiroli, Diego Della Mina
  • SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE
    Publication number: 20130301330
    Abstract: A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines.
    Type: Application
    Filed: May 7, 2013
    Publication date: November 14, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Yasuhiro MATSUMOTO, Noriaki MOCHIDA, Takeshi OHGAMI, Daiki IZAWA