Patents Assigned to Freescale
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Patent number: 8946833Abstract: A pressure sensor includes a first housing having a cavity. The pressure sensor further includes a pressure sensing device attached to a bottom of the cavity. The pressure sensor further includes a layer of gel over the pressure sensing device. The pressure sensor further includes a baffle in contact with the gel to reduce movement of the gel.Type: GrantFiled: October 22, 2012Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Leo M. Higgins, III
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Patent number: 8946000Abstract: A back-end-of-line thin ion beam deposited fuse (204) is deposited without etching to connect first and second last metal interconnect structures (110, 120) formed with last metal layers (LM) in a planar multi-layer interconnect stack to programmably connect separate first and second circuit connected to the first and second last metal interconnect structures.Type: GrantFiled: February 22, 2013Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Douglas M. Reber, Mehul D. Shroff, Edward O. Travis
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Patent number: 8948387Abstract: A communication system has a first and a second communicating device operable to send and receive data units through a communication channel. Some of the data are encrypted using a security key. The first device comprises a first key generator generating a first embodiment of the key independently of a second embodiment of the key generated by a second generator of the second device, the second embodiment being generated independently of the first, which depends on parameter(s) characterizing a first transmission quality of the channel when receiving a first set of unencrypted data sent by the second device. The second embodiment depends on parameter(s) characterizing a second transmission quality of the channel when receiving a second set of unencrypted data sent by the first device, the first set being different from the second set.Type: GrantFiled: August 21, 2008Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Elvis Gabriel Nica
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Patent number: 8945989Abstract: A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads.Type: GrantFiled: June 1, 2014Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Kesvakumar V. C. Muniandy, Navas Khan Oratti Kalandar
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Patent number: 8946041Abstract: Embodiments for forming improved bipolar transistors are provided, manufacturable by a CMOS IC process. The improved transistor comprises an emitter having first and second portions of different depths, a base underlying the emitter having a central portion of a first base width underlying the first portion of the emitter, a peripheral portion having a second base width larger than the first base width partly underlying the second portion of the emitter, and a transition zone of a third base width and lateral extent lying laterally between the first and second portions of the base, and a collector underlying the base. The gain of the transistor is larger than a conventional bipolar transistor made using the same CMOS process. By adjusting the lateral extent of the transition zone, the properties of the improved transistor can be tailored to suit different applications without modifying the underlying CMOS IC process.Type: GrantFiled: June 27, 2012Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kai Zuo
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Patent number: 8947887Abstract: A package assembly comprises an electronic device; a package body; at least a first plurality of leads having a first geometrical shape and a second plurality of leads having a second geometrical shape, protruding from the package body; each of the first plurality of leads being located in corners of the package body; or the first and the second plurality of leads arranged in at least a first row and a second row located in parallel to the first row; each of the rows comprising at least two leads; the first row being transformable into the second row by mirroring the first row along a symmetry plane of the package body; each of the first plurality of leads having the first geometrical shape different from the second geometrical shape.Type: GrantFiled: February 23, 2009Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Robert Bauer, Thorsten Hauck
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Patent number: 8948006Abstract: A cellular communication system includes a method for managing uplink (UL) quality-of-service (QoS) in a two-hop wireless cellular communication system, including determining a count of UL QoS requests received from each user equipment (UE) and determining a served-to-requested ratio that is a ratio of a the number of bytes of UL data served to each UE by a mobile relay to the number bytes of UL data requested by each UE from the mobile relay. A UE subsystem of the mobile relay determines if any UEs are experiencing low UL QoS based on the number of UL QoS requests and the served-to-requested ratio. In response, a macro base station allocates network resources for improving the UL QoS provided to the set of UEs.Type: GrantFiled: January 7, 2013Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Mukesh Taneja
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Patent number: 8947958Abstract: In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold.Type: GrantFiled: October 9, 2012Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Fuchen Mu, Chen He, Peter J. Kuhn
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Patent number: 8949545Abstract: A data processing device includes a load/store module to provide an interface between a processor device and a bus. In response to receiving a load or store instruction from the processor device, the load/store module determines a predicted coherency state of a cache line associated with the load or store instruction. Based on the predicted coherency state, the load/store module selects a bus transaction and communicates it to the bus. By selecting the bus transaction based on the predicted cache state, the load/store module does not have to wait for all pending bus transactions to be serviced, providing for greater predictability as to when bus transactions will be communicated to the bus, and allowing the bus behavior to be more easily simulated.Type: GrantFiled: December 4, 2008Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventor: John D. Pape
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Patent number: 8949551Abstract: In a disclosed embodiment, a data processing system comprises a memory protection unit (MPU); and a plurality of region descriptors associated with the MPU. Each region descriptor is associated with one of multiple subsets of the region descriptors and includes an address range, protection settings, and attributes for a respective region of memory. The subsets include data-only region descriptors, instruction-only region descriptors, and shared region descriptors. The shared region descriptors are used to access memory regions for data and instruction memory requests.Type: GrantFiled: September 30, 2011Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventor: William C. Moyer
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Patent number: 8947940Abstract: A semiconductor device comprises an array of memory cells. Each of the memory cells includes a tunnel dielectric, a well region including a first current electrode and a second current electrode, and a control gate. The first and second current electrodes are adjacent one side of the tunnel dielectric and the control gate is adjacent another side of the tunnel dielectric. A controller is coupled to the memory cells. The controller includes logic to determine when to perform a healing process in the tunnel dielectric of the memory cells, and to apply a first voltage to the first current electrode of the memory cells during the healing process to remove trapped electrons and holes from the tunnel dielectric.Type: GrantFiled: January 30, 2012Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Fuchen Mu, Yanzhuo Wang
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Publication number: 20150029013Abstract: Methods and systems for facilitating viewing of information by machine users associated with machines, such as vehicle users in vehicles, are disclosed. In one example embodiment, a method for facilitating viewing of first information comprises (a) determining second information concerning a viewing direction of the machine user, and (b) adapting at least one operation of at least one display device so as to display the first information. Also, in an additional example embodiment, the method further comprises (c) additionally determining whether a first condition has been met, where the first condition is indicative of whether the machine user has failed to view in a sufficient manner the first information for or during a first predetermined amount of time. Additionally, the method comprises (d), upon the first condition being additionally determined to have been met, one or both of (i) repeating (a), (b), and (c), and (ii) outputting a signal configured to be sensed by the machine user.Type: ApplicationFiled: July 29, 2013Publication date: January 29, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Victor Hugo H. Osornio Lopez, Francisco C. Sandoval Zazueta, Michael A. Staudenmaier
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Publication number: 20150028948Abstract: A device includes a Doherty amplifier. The Doherty amplifier has a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a resistive switch having a first terminal connected to the peaking path and a second terminal connected to a voltage reference, and a controller configured to set the resistive switch to a first resistance value when a power input of the Doherty amplifier is below a threshold and to a second resistance value when the power input of the Doherty amplifier is above the threshold.Type: ApplicationFiled: July 29, 2013Publication date: January 29, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Joseph Staudinger, Paul Hart, Ramanujam Srinidhi Embar, John Vaglica
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Publication number: 20150027198Abstract: A sensor system includes a microelectromechanical systems (MEMS) sensor, control circuit, signal evaluation circuitry, a digital to analog converter, signal filters, an amplifier, demodulation circuitry and memory. The system is configured to generate high and low-frequency signals, combine them, and provide the combined input signal to a MEMS sensor. The MEMS sensor is configured to provide a modulated output signal that is a function of the combined signal. The system is configured to demodulate and filter the modulated output signal, compare the demodulated, filtered signal with the input signal to determine amplitude and phase differences, and determine, based on the amplitude and phase differences, various parameters of the MEMS sensor. A method for determining MEMS sensor parameters is also provided.Type: ApplicationFiled: July 23, 2013Publication date: January 29, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Raimondo P. Sessego, Tehmoor M. Dar, Bruno J. Debeurre
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Publication number: 20150027767Abstract: A method of forming an electronic component includes masking a lead frame to form a mask defining an exposed area, oxidizing the exposed area of the lead frame, wherein the mask inhibits oxidation of an unexposed area, and removing the mask from the lead frame following oxidizing. A lead frame can include a metal sheet patterned to define a pad region and leads. The metal sheet includes metal oxide in a select area. The pad region is substantially free of metal oxide.Type: ApplicationFiled: July 25, 2013Publication date: January 29, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Sheila F. Chopin, Varughese Mathew
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Patent number: 8942655Abstract: An integrated circuit comprising processing logic for operably coupling to radio frequency (RF) receiver circuitry arranged to receive a wireless network signal. The receiver circuitry generates in-phase and quadrature digital baseband representations of the wireless network signal. The processing logic determines quadrature (I/Q) imbalance of the RF receiver circuitry based on the in-phase and quadrature digital baseband representations of the wireless network signal.Type: GrantFiled: May 31, 2007Date of Patent: January 27, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Norman Beamish, Conor O'Keeffe, Patrick Pratt
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Patent number: 8941242Abstract: A method is for forming a decoy via and a functional via. The method includes forming the functional via between a metal portion of a first interconnect layer and a portion of a second interconnect layer. The method further includes forming the decoy via in a protection region between the metal portion of the first interconnect layer and a metal portion of the third interconnect level.Type: GrantFiled: December 7, 2011Date of Patent: January 27, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Mehul D. Shroff, Douglas M. Reber, Edward O. Travis
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Patent number: 8943292Abstract: A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.Type: GrantFiled: October 25, 2006Date of Patent: January 27, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Ravindraraj Ramaraju, David R. Bearden, Prashant U. Kenkare
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Patent number: 8941194Abstract: A pressure sensor device is assembled by forming cavities on a surface of a metal sheet and then forming an electrically conductive pattern having traces and bumps over the cavities. An insulating layer is formed on top of the pattern and then processed to form exposed areas and die attach areas on the surface of the metal sheet. The exposed areas are plated with a conductive metal and then electrically connected to respective ones of the bumps. A gel is dispensed on the die attach areas and sensor dies are attached to respective die attach areas. One or more additional semiconductor dies are attached to the insulating layer and bond pads of these dies are electrically connected to the exposed plated areas. A molding compound is dispensed such that it covers the sensor die and the additional dies. The metal sheet is removed to expose outer surfaces of the bumps.Type: GrantFiled: August 27, 2013Date of Patent: January 27, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Wai Yew Lo, Fui Yee Lim
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Patent number: 8942682Abstract: A network element comprises a radio frequency (RF) transceiver module and a signal processing module operably coupled to the RF transceiver module and arranged to enable at least one telephony connection to be established over a first communication network between the network element and a plurality of local wireless communication units. The signal processing module is further arranged to enable a piconet to be established where the piconet comprises the network element and the plurality of wireless communication units. The signal processing module is further arranged to establish a common telephony connection between the piconet and at least one remote device over a second communication network.Type: GrantFiled: January 22, 2010Date of Patent: January 27, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Steven Wilson