Patents Assigned to Freescale
  • Publication number: 20140380017
    Abstract: A method of managing a memory of an apparatus includes maintaining a plurality of lists of identifiers that each has an associated size value, wherein each identifier identifies a corresponding region of the memory that had been allocated for a process but that is currently not required by any of the one or more processes. When a process requests allocation of a region of the memory: one of the lists is identified that has an associated size value suitable for the allocation request; and if that list is not empty, a region of the memory is identified to the process by one of the identifiers that identifier is removed from that list, and, otherwise, a region of the memory is allocated with a size of the identified associated size value and the allocated region of the memory is identified the process.
    Type: Application
    Filed: September 12, 2014
    Publication date: December 25, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: JEAN-LUC ROBIN, JOSE MENDES-CARVALHO
  • Publication number: 20140374849
    Abstract: An angular rate sensor includes a substrate, a drive mass flexibly coupled to the substrate, and a sense mass suspended above the substrate and flexibly coupled to the drive mass via flexible support elements. An electrode structure is mechanically coupled to, but electrically isolated from, the drive mass and is spaced apart from the substrate so that it is not in contact with the substrate. The electrode structure is configured to produce a signal that indicates movement of the sense mass relative to the electrode when the sensor is subjected to angular velocity. When the angular rate sensor experiences quadrature error, the drive mass, the sense mass, and the electrode structure move together relative to the sense axis. Since the sense mass and the electrode structure move together in response to quadrature error, there is little relative motion between the sense mass and the electrode structure so that quadrature error is largely eliminated.
    Type: Application
    Filed: June 24, 2013
    Publication date: December 25, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Yizhen Lin
  • Publication number: 20140375341
    Abstract: An electronic apparatus includes a semiconductor substrate, outer and inner guard rings disposed along a periphery of the semiconductor substrate, and first and second contact pads electrically coupled to the outer and inner guard rings, respectively. The outer and inner guard rings are electrically coupled to one another to define a conduction path between the first and second contact pads. Each of the outer and inner guard rings includes an Ohmic metal layer having a plurality of gaps and further includes conductive bridges across the gaps. The gaps of the outer guard ring are laterally offset from the gaps of the inner guard ring such that the Ohmic metal layers of the outer and inner guard rings laterally overlap.
    Type: Application
    Filed: June 20, 2013
    Publication date: December 25, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jason R. Fender, Ngai Ming Lau
  • Publication number: 20140380258
    Abstract: A method of performing layout verification for an integrated circuit (IC) layout is described. The method comprises receiving layout information for the IC layout, identifying at least one IC component within the IC layout, extracting localised layout information for the at least one IC component from the received layout information, defining the localised layout information for the at least one IC component within at least one component instance parameter therefor, and performing at least one layout verification check for the at least one component based at least partly on the at least one component instance parameter.
    Type: Application
    Filed: February 23, 2012
    Publication date: December 25, 2014
    Applicant: Freescale Semiconductor, Inc
    Inventors: Xavier Hours, Shitiz Arora, Robert Scott Ruth
  • Publication number: 20140376317
    Abstract: Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.
    Type: Application
    Filed: September 14, 2014
    Publication date: December 25, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Walter L. Terçariol, Richard Titov Lara Saez, Afrânio Magno da Silva, JR.
  • Patent number: 8915116
    Abstract: A mechanism by which a MEMS gyroscope sensor can be calibrated using data gathered from other sensors in a system incorporating the MEMS gyroscope sensor is provided. Data gathered from an accelerometer and a magnetometer in fixed orientation relative to the gyroscope is used to calculate changes in orientation of a system. A constant acceleration vector measured by the accelerometer and a constant magnetic vector measured by the magnetometer are used as reference vectors in a solution to Wahba's problem to calculate a rotation matrix providing the system's orientation with respect to those two constant vectors. By comparing changes in orientation from one time to a next time, measured rates of angular change can be calculated. The measured rates of angular change can be used along with observed gyroscope rates of angular change as input to a linear regression algorithm, which can be used to compute gyroscope trim parameters.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: December 23, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Michael E. Stanley
  • Patent number: 8916421
    Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: December 23, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhiwei Gong, Navjot Chhabra, Glenn G. Daves, Scott M. Hayes
  • Patent number: 8918707
    Abstract: A technique for injecting errors into a codeword includes generating a codeword that includes data bits and one or more checkbits. One or more bit errors are injected into the codeword by modifying at least one of the one or more checkbits.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: December 23, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: William C. Moyer
  • Patent number: 8917204
    Abstract: An integrated circuit for cancelling a radio frequency transmit leakage signal comprises: a transmitter portion comprising at least one amplifier stage for transmitting a radio frequency signal to an antenna port; and a first coupler arranged to operably couple the transmitter portion, the antenna port and a receiver portion. The receiver portion is arranged to receive a first composite signal that comprises a received radio frequency signal from the antenna port and the transmit leakage signal.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: December 23, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Saverio Trotta, Bernhard Dehlink, Ralf Reuter
  • Patent number: 8918591
    Abstract: A data processing system includes a system interconnect, a processor coupled to the system interconnect, and a cache coherency manager (CCM) coupled to the system interconnect. The processor includes a cache. A method includes generating, by the CCM, one or more snoop requests to the cache of the processor; storing the one or more snoop requests to the cache of the processor into a snoop queue; setting a cache enable indicator to indicate that the cache of the processor is to be disabled; in response to setting the cache enable indicator to indicate that the cache of the processor is to be disabled, selectively invalidating the one or more snoop requests to the cache of the processor, wherein the selectively invalidating is performed based on an invalidate snoop queue indicator of the processor; and disabling the cache.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: December 23, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: William C. Moyer
  • Patent number: 8917136
    Abstract: A charge pump system includes a charge pump, a switchable impedance, a comparator, and a capacitor. The switchable impedance has an input coupled to the output of the charge pump. The comparator has a first input coupled to the output of the switchable impedance, a second input coupled to a reference, and an output coupled to the input of the charge pump. The capacitor has a first terminal coupled to the output of the charge pump and a second terminal coupled to the first input of the comparator. The switchable impedance causes a first impedance between the first and second terminals of the capacitor during a start-up operation of the charge pump system and a second impedance between the first and second terminals of the capacitor during a steady-state operation of the charge pump system, wherein the first impedance is lower than the second impedance.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: December 23, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Perry H. Pelley, Michael G. Neaves, Ravindraraj Ramaraju
  • Publication number: 20140367830
    Abstract: An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Rouying Zhan, Chai Ean Gill
  • Publication number: 20140367239
    Abstract: A capacitive keypad position sensor includes a keypad touch panel having a first defined key area disposed in a plane having first and second orthogonal axes. First and second electrodes respectively occupy first and second areas below the first defined key area. Each electrode includes a plurality of parallel rows extending along the first axis and spaced apart from one another along the second axis. Each of the plurality of rows has a length along the first axis that is substantially equal to a width of the first defined key area along the first axis measured at a position along the second axis corresponding to the respective one of the plurality of rows. At least some of the first and second pluralities of rows are interleaved with one another.
    Type: Application
    Filed: March 31, 2014
    Publication date: December 18, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Changchao Shi, Yonggang Chen, Dechang Wang
  • Patent number: 8912569
    Abstract: A hybrid transistor (58) has a substrate (42) with a first (e.g., P type) well region (46) and a second (e.g., N type) well region (44) with an NP or PN junction (43) therebetween. A MOS portion (70-3) of the hybrid transistor (58) has an (e.g., N type) source region (48) in the first well region (46) and a gate conductor (52) overlying and insulated from the well regions (46, 44) that extends laterally at least to the junction (43). A drain or anode (D/A) portion (71-3) in the second well region (44) collects current 56 from the source region (48), and includes a bipolar transistor (78) having an (e.g., N+) emitter region (64), a (e.g., P type) base region (59) and a (e.g., N type) collector region (62) laterally separated from the junction (43). Different LDMOS-like or IGBT-like properties are obtained depending on whether the current 56 is extracted from the hybrid transistor (58) via the bipolar transistor (78) base (59) or emitter (64) or both.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Vishal P. Trivedi
  • Patent number: 8914550
    Abstract: A data processing device includes a plurality of devices, a processor core, a memory, and a queue manager. The processor core stores one or more commands in a command queue of the memory to be executed by the plurality of devices to implement a data transfer path. The queue manager stores a frame queue for each of the plurality of devices. Each frame queue includes a first field having a pointer to an address of the command queue, and a second field to identify a next-in-sequence frame queue. A first device stores a data descriptor in the frame queue of the second device to initiate a data transfer from the first device to the second device. The data descriptor includes a field to indicate an offset value from the address of the command queue to a location of a command to be executed by the second device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tommi M. Jokinen, David B. Kramer, Kum Xu
  • Patent number: 8913436
    Abstract: A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Padmaraj Sanjeevarao, David W. Chrudimsky
  • Patent number: 8914712
    Abstract: A data processing device can perform error detection and correction in two stages: in the first stage, error detection is performed for the load data using the in-line error detection information. If a first type of error is detected in the data segment, the error is corrected using the in-line error detection information. If a second type of error is detected error correction is performed using the residual sum.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: December 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, Ajay J. Joshi, Bobak A. Nazer
  • Patent number: 8912667
    Abstract: A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: December 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert J. Wenzel, Kevin J. Hess, Chu-Chung Lee
  • Patent number: 8912857
    Abstract: A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: December 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hugues Beaulaton, Thierry Cassagnes, Stéphane Colomines, Didier Salle
  • Patent number: 8913634
    Abstract: A system comprises a pulse generator 615 configured to provide a control pulse a transmission gate 603 configured to interrupt a path between a communication device 307 and an auxiliary device 303 during the control pulse; and a pulse transmitter 607 responsive to the control pulse and configured to inject an interrupt pulse in the path while the path is interrupted. A corresponding method of providing an interrupt signal in an audio path between a source and a sink includes interrupting an audio path between the source and the sink, injecting an interrupt pulse in the audio path while the audio path is interrupted, and then reconnecting the audio path.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: December 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Alan Ruff