Abstract: A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.

Abstract: An electronic device module as described herein includes an electronic device package having device contacts. The electronic device module can be manufactured by providing an electrically conductive ground plane having a device opening for an electronic device package, and having an antenna ground section. The manufacturing method continues by embedding the ground plane and the electronic device package in encapsulating material such that device contacts of the electronic device package and a first side of the ground plane reside at a device mounting surface. Thereafter, an antenna circuit structure is formed overlying the device mounting surface. The antenna circuit structure includes an antenna signal element that cooperates with the antenna ground section to form an integrated antenna for the electronic device module.

Abstract: An electronic device (50) having a conductive substrate via (70) extending between a conductor (39) on a rear face (22) and a conductor (58) over the front surface (23) of the substrate (21) includes a multi-layered etch-stop (56, 56-2) beneath the front surface conductor (58). The etch-stop (56, 56-2) permits use of a single etchant to penetrate both the substrate (21) and any overlying semiconductor (44) and/or dielectric (34) without attacking the overlying front surface conductor (58). This is especially important when the semiconductor (44) and dielectric (34) are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop (56) is preferably a stack (63, 73) of N?2 pairs (62-i) of sub-layers (62-i1, 62-i2) in either order, where a first sub-layer (62-i1) comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer (62-i2) comprises etch resistant material (e.g., Ni).

Abstract: A technique for performing adaptive predistortion in a transmitter includes receiving, at a first input of an error signal unit, a delayed version of a baseband input signal. The technique also includes receiving, at a second input of the error signal unit, a power amplifier feedback signal from an output of a power amplifier. An input error signal that corresponds to a difference between the delayed version of the baseband input signal and the power amplifier feedback signal is then provided at an output of the error signal unit. The input error signal is then received at an input of a signal conditioner. An adjusted error signal that has a lower direct current offset than the input error signal is provided at an output of the signal conditioner.

Abstract: A method for calculating backward state metrics of a trellis, the method includes: performing a radix-K calculation of backward state matrices of multiple states of at least one time instance of a trellis; and performing a radix-J calculation of backward state matrices of multiple states of at least one other time instance of the trellis; wherein K differs from J.

Abstract: A PWM controller for adjusting an output voltage of a buck and boost converter includes a first saw wave generator, which generates a first saw wave in accordance with the level of the output voltage. A first comparator coupled to the first saw wave generator compares the first saw wave with a first reference voltage and generates a first pulse. A peak hold circuit coupled to the first saw wave generator holds a peak value of the first saw wave. A second saw wave generator coupled to the peak hold circuit generates a second saw wave having a lower limit value that is the peak value of the first saw wave. A second comparator coupled to the second saw wave generator compares the second saw wave with the first reference voltage and generates a second pulse.

Abstract: Apparatus and methods are provided for utilizing a plurality of processing units. A method comprises selecting a pending job from a plurality of unassigned jobs based on a plurality of assigned jobs for the plurality of processing units and assigning the pending job to a first processing unit. Each assigned job is associated with a respective processing unit, wherein the pending job is associated with a first segment of information that corresponds to a second segment of information for a first assigned job. The method further comprises obtaining the second segment of information that corresponds to the first segment of information from the respective processing unit associated with the first assigned job, resulting in an obtained segment of information and performing, by the first processing unit, the pending job based at least in part on the obtained segment of information.

Abstract: A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a functional mode; coupling, by the switching circuit, a third power grid to a first power grid; supplying power from the first power source to the SRPG circuit via the first power grid, the switching circuit and the third power grid; supplying power from a second power source to a second circuit via a second power grid; sending to the switching circuit, to the SRPG circuit and to the first power source a control signal indicating that the SRPG circuit should operate in a state retention mode; coupling, by the switching circuit, the third power grid to the second power grid; supplying power from the second power source to the SRPG circuit via the second power grid, the switching circuit and the third power grid; supplying power from the second power source to the second circuit vi

Abstract: A method for providing data protection for data stored within a Random Access Memory element. The method comprises receiving data to be written to memory, dividing the received data into a plurality of data sections, applying error correction codes to the data sections to form codeword sections, interleaving the codeword sections to form an interleaved data codeword, and writing within a single clock cycle the interleaved data codeword to memory.

Abstract: An integrated circuit device comprises at least one clock monitor. The at least one clock monitor comprises a timer arranged to receive a clock signal, generate a first timing signal arranged to toggle between states in response to a trigger edge of the clock signal, and generate a second timing signal arranged to toggle between states in response to a trigger edge of the clock signal such that a state transition of the second timing signal in response to a trigger edge of the clock signal is delayed by a period T with respect to the trigger edge of the clock signal in response to which that transition occurs. The at least one clock monitor further comprises a detector arranged to receive at a first input thereof the first timing signal, receive at a second input thereof the second timing signal, compare states of the first and second timing signals, and configure an indication of a timing discrepancy based at least partly on the comparison of the first and second timing signals.

Abstract: A method for compensating for variations in timing of data sent to a processor on data bit lines relative to a strobe clock sent to the processor on a strobe clock line that can be used in a dual data rate (DDR) memory identifies discrete minimum and maximum time offset values for test data in selected data bit patterns for the data bit lines. The discrete minimum time offset value is the minimum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock and the discrete maximum time offset value is a maximum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock. The discrete minimum and maximum time offset values identify a valid range when the data bit lines supply data in a steady-state condition for latching into the processor by the strobe clock.

Abstract: A semiconductor process and apparatus includes forming first and second gate electrodes (151, 161) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). Either or both of the high-k gate dielectric layers (121, 122) may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g., 14). As deposited, the initial layer (14) has an exposed surface (18) and an initial predetermined crystalline structure. An exposed thin surface layer (20) of the initial layer (14) is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.

Abstract: A system has a pipelined processor for executing a plurality of instructions by sequentially fetching, decoding, executing and writing results associated with execution of each instruction. Debug circuitry is coupled to the pipelined processor for monitoring execution of the instructions to determine when a debug event occurs. The debug circuitry generates a debug exception to interrupt instruction processing flow. The debug circuitry has control circuitry for indicating a number of instructions, if any, that complete instruction execution between an instruction that caused the debug event and a point in instruction execution when the exception is taken.

Abstract: A clock signal generating arrangement for a communication device generates a system clock signal at an output for use as a timing reference. The clock signal generating arrangement comprises a reference clock generator for generating a reference clock signal, a main clock generator for generating a main clock signal having a greater accuracy than the reference clock signal, a clock adjust circuit coupled to the reference clock generator for generating a compensated reference clock signal to compensate for error in the reference clock signal and a clock signal selector coupled to the reference clock generator the main clock generator and the clock adjust circuit.

Abstract: A wireless transmitter exhibits improved power de-rating reduction, which improves the power efficiency of non-constant envelop communication systems by mapping N first samples of a first discrete Fourier transform (DFT) of a group of coded symbols to M sub-carriers according to a first sub-carrier mapping rule (212), performing a first inverse DFT (IDFT) on the M sub-carriers to provide M second samples (214), clipping the M second samples according to a clipping rule to provide M third samples (216), performing a second DFT on the M third samples (218), and applying a frequency domain mask to generate M clipped samples (220) which may be mapped to O subcarriers according to a predetermined second subcarrier mapping rule. The transmitter may be advantageously implemented within a single carrier transmission scheme, such as a single carrier-frequency division multiple access (SC-FDMA) uplink transmission scheme.

Abstract: A bus driver has a ground terminal and a first and a second terminal. In a first operation mode the bus driver provides at the first terminal a first output voltage comprising a first data signal; and at the second terminal the bus driver provides a second output voltage comprising a second data signal. In a second operation mode the bus driver provides at the first terminal a first output voltage comprising a third data signal; and at the second terminal the bus driver provides a second output voltage, wherein a curve of the second output voltage is synchronous however inverted in relation to a curve of the first output voltage. An engine comprises a bus driver as set out above.

Abstract: A device includes a current source circuit to separately provide a first current and a second current and a thermal detection device coupleable to the output of the current source circuit. The device further includes a voltage detection circuit to provide a first indicator of a first voltage representative of a voltage at the thermal detection device in response to the second current and a second indicator of a second voltage representative of a voltage difference between the voltage at the thermal detection device in response to the second current and a voltage at the voltage detection device in response to the first current. The device further includes a temperature detection circuit to provide an over-temperature indicator based on the first indicator and the second indicator, wherein an operation of a circuit component of the device can be adjusted based on the over-temperature indicator.

Abstract: A method is provided for error correction of a memory. The method includes: providing a first memory and a second memory; initiating a read operation of the first memory to retrieve data; performing an error correction code (ECC) processing on the data, wherein the ECC processing for determining that at least a portion of the data is erroneous and for providing corrected data; and determining if an address of the erroneous data is stored in the second memory, if the address of the erroneous data is stored in the second memory, storing the corrected data in the second memory, and if the address of the erroneous data is not stored in the second memory, storing the address in the second memory.

Abstract: A method for generating a debug message includes receiving a translated address and an untranslated address associated with a same processor operation, determining a value of one or more control indicators, selecting the translated address or the untranslated address as a selected address based on the value of the one or more control indicators, and creating a debug message using at least a portion of the selected address.

Abstract: Embodiments of apparatus and methods for applying a gain to an input signal are provided. An embodiment of a switched-capacitor gain stage circuit includes an input node, an output node, an operational amplifier, a correlated-double-sampling portion, a correlated-level-shifting portion, and a switching configuration. The operational amplifier has a first amplifier input, a second amplifier input, and an amplifier output. The correlated-double-sampling portion includes a plurality of sampling capacitors arranged in parallel and selectively coupled between the input node and a central node, and an offset storage capacitor including a first terminal coupled to the first amplifier input. The correlated-level-shifting portion includes a correlated-level-shifting capacitor including a first terminal coupled to the output node.