Patents Assigned to Freescale
  • Method and apparatus for calculating sensor modelling coefficients
    Patent number: 8942958
    Abstract: A method of calculating at least one sensor modelling coefficient for multiple sensor regions of operation includes defining a first sensor region of operation and a further sensor region of operation, and calculating the sensor modelling coefficient for the first sensor region of operation. A derivative equation then is derived for the further sensor region of operation based at least partly on at least one defined inter-region boundary constraint. The sensor modelling coefficient is calculated for the further sensor region of operation based at least partly on the derivative equation.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: January 27, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Mahendra Pal Singh
  • Transmission and reception channel selection for communicating between a transmitter unit and a receiver unit
    Patent number: 8942186
    Abstract: A data communication network. The network includes a transmitter unit for transmitting data and a receiver unit for receiving data from the transmitter unit. The network has two or more data channels via which data may be transmitted by the transmitter unit to the receiver unit. The receiver unit includes a receiver channel selection unit for selecting a reception channel from the at least two data channels. The receiver channel selection unit operates independent from a selection of a transmission channel by a transmission channel selection unit in the transmitter unit. The transmission channel selection unit is arranged to select a transmission channel from the at least two data channels to transmit data to the receiver unit.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: January 27, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ionut-Gabriel Dinulescu, Bogdan Hobinca, Mitsunobu Matsuka, Koichi Matsuo, Nicusor Penisoara
  • Master-slave flip-flop with low power consumption
    Patent number: 8941429
    Abstract: In a master-slave flip-flop, the master latch has first and second three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock switches having opposite phases are provided. The first clock switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock switch. The second clock switch is configured in one of the second and third three-state stages, and the other stage shares the second clock switch. The second three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock switch power consumption.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: January 27, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Zhihong Cheng
  • Configurable flip-flop
    Patent number: 8941427
    Abstract: A configurable flip-flop can be operated in a normal mode and a buffer mode. In the normal mode, the flip-flop latches data at the flip-flop input based on a clock signal. In the buffer mode, the flip-flop provides data at the flip-flop input to the flip-flop output, independent of the clock signal.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 27, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shayan Zhang, Ravindraraj Ramaraju
  • Integrated circuit, communication unit and method for phase adjustment
    Patent number: 8941534
    Abstract: An integrated circuit for phase shifting a radio frequency signal, wherein the integrated circuit comprises at least one phase shifter comprising: at least one input for receiving a radio frequency signal, a voltage variable element; and a plurality of active devices operably coupled to the voltage variable element and arranged to receive a variable control voltage. The plurality of active devices comprise at least two active devices coupled in a common base arrangement and arranged to receive the radio frequency signal with the voltage variable element coupling the emitter contacts or source contacts of the at least two active devices, such that a variable control voltage applied to the voltage variable element adjusts a phase of the radio frequency signal.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: January 27, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Ralf Reuter
  • BACKSCATTERING FOR LOCALIZED ANNEALING
    Publication number: 20150021746
    Abstract: A method of fabricating an electronic apparatus includes forming an active layer over a wafer, forming a backscatter layer over the wafer, and directing radiation toward the wafer to anneal the active layer. The backscatter layer is not transparent to the radiation, more reflective than absorptive of the radiation, and positioned such that the backscatter layer inhibits exposure of the wafer to the radiation apart from the active layer.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 22, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Nirmal David Theodore
  • SEMICONDUCTOR SENSOR DEVICE WITH FOOTED LID
    Publication number: 20150024535
    Abstract: A semiconductor sensor device is packaged using a footed lid instead of a pre-molded lead frame. A semiconductor sensor die is attached to a first side of a lead frame. The die is then electrically connected to leads of the lead frame. A gel material is dispensed onto the sensor die. The footed lid is attached to the substrate such that the footed lid covers the sensor die and the electrical connections between the die and the lead frame. A molding compound is then formed over the substrate and the footed lid such that the molding compound covers the substrate, the sensor die and the footed lid.
    Type: Application
    Filed: October 8, 2014
    Publication date: January 22, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Wai Yew Lo
  • DEBUGGING METHOD AND COMPUTER PROGRAM PRODUCT
    Publication number: 20150026523
    Abstract: A method for debugging a computer program is proposed. The method comprises: running at least part of said computer program on a computer, thereby prompting said computer to execute a sequence of instructions and to generate a trace corresponding to said executed sequence of instructions; and, when said program has generated an exception, selecting a set of one or more exception strings on the basis of said trace, so that each of said exception strings is a unique substring of said trace; and indicating said exception strings to a user or to a debugging tool. The set of exception strings may notably include the ultimate shortest unique substring of said trace. A computer program product is also described.
    Type: Application
    Filed: February 29, 2012
    Publication date: January 22, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Alexandru Ghica, Razvan Ionescu, Radu-Victor Sarmasag
  • WIRE BONDING CAPILLARY WITH WORKING TIP PROTRUSION
    Publication number: 20150021376
    Abstract: A method for bonding a wire to a substrate includes forming a wire ball at a working tip of a capillary and contacting the wire ball to a substrate via the capillary. The method also includes driving a protrusion at the working tip of the capillary into contact with a region of the substrate surrounding the wire ball. A capillary for wire bonding includes a working face, an annular chamfer section, and a cylindrical bore offsetting the annular chamfer section from the working face. A capillary for wire bonding includes a capillary body comprising a working tip having a working face. The capillary body defines an axial passage extending from the working face along a longitudinal axis of the capillary. The axial passage includes a cylindrical bore extending internally from the working face, and a first annular chamfer having a major diameter defined by the cylindrical bore.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Trent Uehling, Ilko Schmadlak
  • Cryptographic key derivation device and method therefor
    Patent number: 8938072
    Abstract: A data processing system includes a cryptographic processing module providing for cryptographic key generation. A method entails computing derived keys one time, during a first execution of a key generation process, such that they may subsequently be utilized for processing large quantities of data without being re-computed. The derived keys provide for the efficient cryptographic processing of data, including data frames.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 20, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Srdjan Coric, Steven D. Millman
  • Memory device redundancy management system
    Patent number: 8937845
    Abstract: A system for managing redundancy in a memory device includes memory arrays and associated periphery logic circuits, and redundant memory arrays and associated redundant periphery logic circuits. The memory arrays and a first set of logic circuits associated with the periphery logic circuits corresponding to the memory arrays are connected to the power supply by way of memory I/O switches. The redundant memory arrays and associated redundant periphery logic circuits are connected to the power supply by way of redundant I/O switches. The memory and redundant I/O switches are switched on/off based on an acknowledgement signal generated during a built-in-self-test (BIST) operation of the memory device.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: January 20, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chetan Verma, Piyush Kumar Mishra, Ashish Sharma
  • Electrostatic occupant detection system
    Patent number: 8937478
    Abstract: An electrostatic occupant detection system includes an electrostatic sensor and an electronic control unit. The electronic control unit is switchable between an occupant determination state in which the electronic control unit outputs a sine wave having a constant amplitude and a diagnosis state in which the electronic control unit maintains a voltage of the electrostatic sensor at a constant level. The electronic control unit gradually changes at least one of an amplitude and a frequency of the sine wave either when the electronic control unit switches from the occupant determination state to the diagnosis state and/or when the electronic control unit switches from the diagnosis state to the occupant determination state.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: January 20, 2015
    Assignees: Denso Corporation, Freescale Semiconductor, Inc.
    Inventors: Ryo Shimizu, Craig M. Aykroyd, John M. Pigott
  • METHOD OF DETECTING IRREGULAR CURRENT FLOW IN AN INTEGRATED CIRCUIT DEVICE AND APPARATUS THEREFOR
    Publication number: 20150015240
    Abstract: A method of detecting irregular high current flow within an integrated circuit (IC) device is described. The method comprises obtaining infrared (IR) emission information for the IC device, identifying at least one functional component within the IC device comprising a high current flow, based at least partly on the obtained IR emission information, obtaining IR emission information for at least one reference component within the IC device, and determining whether the high current flow of the at least one functional component comprises an irregular high current flow based at least partly on a comparison of respective IR emission information for the at least one functional component and the at least one reference component.
    Type: Application
    Filed: February 27, 2012
    Publication date: January 15, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Anton Rozen, Leonid Fleshel, Michael Priel, Yoav Weizman
  • Lead frame with power bar for semiconductor device
    Patent number: 8933547
    Abstract: A lead frame for a packaged semiconductor device has multiple, configurable power bars that can be selectively electrically connected, such as with bond wires, to each other and/or to other leads of the lead frame to customize the lead frame for different package designs. One or more of the configurable power bars may extend into one or more cut-out regions in a die paddle of the lead frame, which allows for short bond wires to be used to connect the power bars to die pads of a semiconductor die mounted on the die paddle.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jia Lin Yap, Yin Kheng Au, Ahmad Termizi Suhaimi, Seng Kiong Teng, Boon Yew Low, Navas Khan Oratti Kalandar
  • Capacitive sensor radiation measurement
    Patent number: 8933711
    Abstract: A system that includes at least one capacitive sensor for least one angle of incidence component of radiation being measured striking the sensor. The measured capacitance of the sensor is affected by radiation striking the sensor. In some embodiments, the system includes multiple sensors where differences in the capacitive measurements of the sensors can be used to determine information about the radiation such as e.g. horizontal angle, directional angle, and dose.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Method and apparatus for filtering trace information
    Patent number: 8935577
    Abstract: In a processing system comprising a plurality of data processors at an integrated circuit die, each data processor has a local debug module. In response to acquiring data trace information based upon a corresponding local filtering criteria, the local debug modules transmit their data trace information to a global resource from each of the local debug modules for further filtering by a common filtering criteria.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gary L. Miller, Mark Maiolani
  • Compiler optimized safety mechanism
    Patent number: 8935679
    Abstract: An approach is provided in which a set of common instructions are each executed by at least two processor cores. Each of the processor cores queues values resulting from at least one of the common instructions (a critical section). The queued values are compared by a queued comparator. An exception is issued in response to the comparison revealing unequal values having been queued by the processor cores.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gary R. Morrison, Brian C. Kahne, Anthony M. Reipold
  • Binary adder and multiplier circuit
    Patent number: 8933731
    Abstract: An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rohit Goyal, Amit Kumar Dey, Naman Gupta
  • Power MOSFET structure and method
    Patent number: 8932928
    Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Peilin Wang, Edouard D. de Fresart, Wenyi Li
  • System and method for performing scan test
    Patent number: 8935584
    Abstract: A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Guoping Wan, Shayan Zhang, Wanggen Zhang