Abstract: A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

Abstract: A method of detecting a set up signal having a predetermined frequency and used for data transmissions over a communication network comprises comparing an energy level of a filtered received signal with a first predetermined value and providing a first detect signal, comparing an energy level of a component of the received signal at a predetermined frequency with a second predetermined value and providing a second detect signal. In addition, an autocorrelation function is performed on the received signal to discriminate between the set up signal and other signals in the received signal, and a check signal is provided when the autocorrelation function identifies the set up signal. The set up signal in the received signal is detected in response to the first and the second detect signals and the check signal. A method of detecting phase reversals in the set up signal is also disclosed.

Abstract: A method includes forming a first conductive layer over a substrate in a first region and second region of the substrate; patterning the first conductive layer to form a select gate in the first region and to remove the first conductive layer from the second region; forming a charge storage layer over the select gate and the substrate in the first region and over the substrate in the second region; forming a second conductive layer over the charge storage layer in the first and second regions; and patterning the second conductive layer and charge storage layer to form a control gate overlapping the select gate in the first region, wherein a first portion of the charge storage layer remains between the select gate and control gate, and to form an electrode in the second region, wherein a second portion of the charge storage layer remains between the electrode and substrate.

Abstract: A testing circuit in an integrated circuit indirectly measures a voltage at a node of other circuitry in the integrated circuit. The testing circuit includes a transistor having a control electrode, a first conducting electrode coupled to a first pad, a second conducting electrode coupled to a terminal of a power supply, and one or more switches for selectively coupling the control electrode to one of the node and a second pad. A method includes determining a relationship between drain current and gate voltage of the transistor when the control electrode is coupled to the second pad. A voltage at the node is determined by relating the current through the first conducting electrode of the transistor when control electrode is coupled to the node.

Abstract: A method of fabricating a microelectromechanical (MEMS) device includes bonding a transducer wafer to a substrate wafer along a bond interface. An unpatterned transducer layer included within the transducer wafer is patterned. A release etch process is then performed during which a sacrificial layer is exposed to a selected release etchant to remove at a least a portion of the sacrificial layer through the openings in the patterned transducer layer. A release etch stop layer is formed between the sacrificial layer and the bond interface prior to exposing the sacrificial layer to the release etchant. The release etch stop layer prevents the ingress of the selected release etchant into the region of the MEMS device containing the bond interface during the release etch process.

Abstract: A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a voltage potential across the RRAM storage cells.

Abstract: A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. A die is attached to the die mounting substrate with die connection pads. Bond wires selectively electrically couple the die connection pads to the external leads and the bonding pads and electrically conductive external protrusions are mounted to the external connection pads. An encapsulant covers the die and bond wires. The external protrusions are located at a central region of a surface mounting side of the package and the external leads project outwardly from locations near the die support towards peripheral edges of the package.

Abstract: A MEMS device (40) includes a base structure (42) and a microstructure (44) suspended above the structure (42). The base structure (42) includes an oxide layer (50) formed on a substrate (48), a structural layer (54) formed on the oxide layer (50), and an insulating layer (56) formed over the structural layer (54). A sacrificial layer (112) is formed overlying the base structure (42), and the microstructure (44) is formed in another structural layer (116) over the sacrificial layer (112). Methodology (90) entails removing the sacrificial layer (112) and a portion of the oxide layer (50) to release the microstructure (44) and to expose a top surface (52) of the substrate (48). Following removal, a width (86) of a gap (80) produced between the microstructure (44) and the top surface (52) is greater than a width (88) of a gap (84) produced between the microstructure (44) and the structural layer (54).

Abstract: A memory is disclosed that includes a plurality of memory cells, a plurality of sense amplifiers for reading data of the memory cells, and a voltage regulator coupled to the plurality of sense amplifiers. The voltage regulator includes a reference sense amplifier, a current injector, and a current injector control circuit. The current injector control circuit controls an amount of current provided by the current injector to an output node of the voltage regulator based on a voltage of the reference sense amplifier.

Abstract: A wireless communication unit comprises a receiver for receiving information from a remote transmitter unit. The receiver comprises a demodulator for demodulating received data packets operably coupled to a decoder arranged to perform a cyclic redundancy check (CRC) on the demodulated received data packets and perform multi-protocol encapsulated (MPE) decoding thereon. The demodulator forwards both valid CRC corrected data packets and non-corrected CRC data packets to the decoder and the decoder is configured to place the MPE non-corrected CRC data packets into Reed Solomon (RS) code words.

Abstract: A MEMS sensor (20, 86) includes a support structure (26) suspended above a surface (28) of a substrate (24) and connected to the substrate (24) via spring elements (30, 32, 34). A proof mass (36) is suspended above the substrate (24) and is connected to the support structure (26) via torsional elements (38). Electrodes (42, 44), spaced apart from the proof mass (36), are connected to the support structure (26) and are suspended above the substrate (24). Suspension of the electrodes (42, 44) and proof mass (36) above the surface (28) of the substrate (24) via the support structure (26) substantially physically isolates the elements from deformation of the underlying substrate (24). Additionally, connection via the spring elements (30, 32, 34) result in the MEMS sensor (22, 86) being less susceptible to movement of the support structure (26) due to this deformation.

Abstract: A method comprises fabricating an interconnect structure comprising a plurality of conductive interconnects encased in a dielectric structure and coupling each of the conductive interconnects to a corresponding bond pad of a package substrate and bond pad of a die. A device package comprises a substrate having a first plurality of bond pads disposed at a first surface of the substrate and a die having a first surface facing the first surface of the substrate and a second surface opposite the first surface, the die comprising a second plurality of bond pads disposed at the second surface. The device package further comprises an interconnect structure comprising a plurality of conductive interconnects encased in a dielectric structure, each of the conductive interconnects coupled to a corresponding bond pad of the first plurality of bond pads and to a corresponding bond pad of the second plurality of bond pads.

Abstract: A mechanism is provided by which signal travel distance within and between semiconductor device packages is reduced and substrate size and complexity can be reduced. This capacity is provided by virtue of a conductive via that intersects a wire bond molded within a package substrate. The via provides a direct electrical connection between an external signal transmitter or receiver and the points connected by the wire bond, and thereby avoiding the need for the signal to transit built up interconnects in the semiconductor device package. Conductive vias can provide connectivity through or to a package substrate, and can be through vias or blind vias. The conductive via is formed by either mechanical or laser drilling, and is filled using standard fill techniques, and is therefore readily incorporated into a package production flow.

Abstract: An ESD protection device, which is arranged to be active at a triggering voltage (Vt1) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth.

Abstract: A semiconductor device comprises a plurality of output pads bondable to an output pin, a plurality of reference pads bondable to a reference pin, and output driver circuitry with a control terminal for receiving a control signal and arranged to drive the plurality of output pads relative to the plurality of reference pads in dependence on the control signal. The output driver circuitry includes driver sections and selection circuitry. Each driver section is arranged to drive an output pad relative to the single reference pad in dependence on a respective section control signal. The reference pads are connected in a one-to-one relationship to the driver sections. The output pads are connected in a one-to-one relationship to the driver sections. The selection circuitry provides the respective section control signals to the driver sections in dependence on at least one selection signal and the control signal.

Abstract: A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array interconnecting the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, the second circuit includes a second wire bond array interconnecting a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds over the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

Abstract: A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.

Abstract: A pipeline circuit determines a first effective address based a sum of a first value and a second value. The first effective address is based upon an actual value of a carry-in into a bit-wise region of the first and second values. The bit-wise region includes a predefined internal region of bits of the first and second values. The pipeline circuit also determines a second effective address based a sum of a third value and a fourth value. A collision detector circuit receives bits from the bit-wise region of each of the four values and determines a plurality of speculative results based upon the bits of the bit-wise regions and based upon a plurality of speculative carry-in values. A collision indicator is asserted based on at least one result of the plurality of speculative results, and the actual values of the first and second carry-in.

Abstract: A DC to DC converter including a buck converter, a boost converter, and a control unit, wherein the control unit is arranged to calculate an error voltage of the buck converter Verr_buck based on a feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the buck converter Vref_buck, and wherein the control unit is arranged to calculate an error voltage of the boost converter Verr_boost based on the feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the boost converter Vref_boost, wherein the reference voltage of the boost converter Vref_boost is shifted by an offset Voffset as compared to the reference voltage of the buck converter Vref_buck.

Abstract: A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.