Abstract: An EDA tool for verifying timing constraints of an integrated circuit (IC) design includes a processor and a memory that stores register transfer level (RTL) code of the IC design and a timing constraint file. The processor generates a netlist based on the RTL code, and identifies asynchronous clock paths, false paths and multi-cycle paths in the netlist using the timing constraint file. The processor then inserts buffer cells for logic cells in the netlist. The processor also inserts buffer cells in the asynchronous clock paths, false paths, and multi-cycle paths. The processor delay annotates logic cells and clock delay cells with a zero delay value and the buffer cells with known delay values. The processor generates a modeled standard delay format (SDF) file and performs a gate level simulation (GLS) using the modeled SDF file.

Abstract: A nonvolatile memory includes a memory array having a plurality of memory cells, a select gate driver configured to provide a select gate voltage to a select gate of a first memory cell of the plurality of memory cells, and a control gate driver configured to use the select gate voltage to provide a control gate voltage to a control gate of a second memory cell of the plurality of memory cells.

Abstract: A memory circuit has control gate circuitry (104) and select gate circuitry (106). A first memory cell (122/124) has a control gate coupled to the control gate circuitry, a select gate coupled to the select gate circuitry, a drain that is coupled to a first bit line for reading a logic state of the of the first memory cell, and a source. A second memory cell (150/152 or 158/160) having a control gate coupled to the control gate circuitry, a select gate coupled to the select gate circuitry, a drain that is coupled to a second bit line for reading a logic state of the of the second memory cell, and a source. A source control circuit (102) that, during programming of the first memory cell, outputs a first voltage to the source of the first memory cell and keeps the source of the second memory cell floating.

Abstract: A microelectromechanical systems (MEMS) die includes a substrate having a recess formed therein and a cantilevered platform structure. The cantilevered platform structure has a platform and an arm extending from the platform, wherein the platform and arm are suspended over the recess. The arm is fixed to the substrate and is a sole attachment point of the platform to the substrate. A MEMS device resides on the platform. Fabrication methodology entails forming the recess in the substrate, with the recess extending inwardly from a surface of the substrate, and attaching a structural layer over the recess and over the surface of the substrate. The MEMS device is formed on the structural layer and the structural layer is removed around a perimeter of the platform and the arm to form the cantilevered platform structure.

Abstract: A system and method of accelerating sparse matrix operations in full accuracy simulation of a circuit includes determining repetitive blocks of the circuit, determining a set of values of a current block, determining whether the state of the current block is sufficiently close to the state of a stored block solution when the corresponding values are within a predetermined error range, and performing a reduced computation using the stored block solution to provide a solution for the current block when the states are sufficiently close to each other. The reduced computation includes retrieving previously stored solutions and performing substantially simplified matrix and vector operations while maintaining accuracy of the solution. Reduced precision versions of the values may be used to generate a hash index used to store the block solutions. Stored redundant device information may also be used to simplify device solutions in a similar manner.

Abstract: A method includes over-programming thin film storage (TFS) memory cells on a semiconductor wafer with a first voltage that is higher than a highest voltage used to program the memory cells during normal operation of the memory cells. With the memory cells in an over-programmed state, the wafer is exposed to a first temperature above a product specification temperature for a period of time sufficient to induce redistribution of charge among storage elements in the memory cells.

Abstract: A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.

Abstract: A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.

Abstract: A programmable buffer system includes a plurality of programmable resources. Each of the programmable resources includes, in an unconfigured state, a buffer with multiple entries, an input multiplexer, and an output multiplexer. Configuration information registers specify whether each of the programmable resources is configured as one of a group consisting of: a logic block, a shift register, and a state record, and which of a plurality of timer signals is to be provided to each of the plurality of programmable resources.

Abstract: A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.

Abstract: Piggy-back snoops are used for non-coherent memory transactions in distributed processing systems. Coherent and non-coherent memory transactions are received from a plurality of processing cores within a distributed processing system. Non-coherent snoop information for the non-coherent memory transactions is combined with coherent snoop information for the coherent memory transactions to form expanded snoop messages. The expanded snoop messages are then output to a snoop bus interconnect during snoop cycles for the distributed processing system. As such, when the processing cores monitor the snoop bus interconnect, the processing cores receive the non-coherent snoop information along with coherent snoop information within the same snoop cycle. While this piggy-backing of non-coherent snoop information with coherent snoop information uses an expanded snoop bus interconnect, usage of the coherent snoop bandwidth is significantly reduced thereby improving overall performance of the distributed processing system.

Abstract: A packaged integrated circuit (IC) device having a heatsink mounted onto an IC die, itself mounted onto a die pad, is assembled using a lead frame having tie bars that deflect during an encapsulation phase of the device assembly, which enables the die pad, the die, and the heatsink to move relative to the lead frame support structure when compressive force is applied by the molding tool. This movement results in negligible relative displacement between the heatsink and the die during encapsulation, which reduces the probability of physical damage to the die. Each tie bar has a number of differently angled sections that enable it to deflect when compressive force is applied to it.

Abstract: There is provided an energy consumption meter device (1) comprising the processor (8) arranged to receive input data from the sampling unit. The processor calculates at a calculation step [n] an energy contribution value using ?E using a sampled voltage value and a sampled current value. The processor will calculate an energy value E[n] using a reminder value which was calculated at a previous calculation step [n?1]. The processor will then calculate a relative delay Td? using the threshold value, the reminder value and the energy value, and generate an output pulse at an output time tpulse which is delayed for the relative delay Td? with respect to the calculation time step[n]. By delaying the output pulse with a value which is a closest proximity of Td, the cycle-by-cycle jitter is less or equal to the clock frequency of the timer tclk.

Abstract: The embodiments described herein provide a radar device and method that can provide improved sensitivity. In general, the embodiments described herein provide a saturation detector and reset mechanism coupled to a radar receiver. The saturation detector is configured to detect saturation events in the radar receiver, and the reset mechanism is configured to reset at least one filter unit in the radar receiver in response to detected saturation events. As such, the embodiments can facilitate improved radar sensitivity by reducing the effects of saturation events in the radar receiver.

Abstract: A semiconductor device includes a substrate, a dielectric layer supported by the substrate, an interconnect adjacent the dielectric layer, the interconnect including a conduction material and a barrier material disposed along sidewalls of the interconnect between the conduction material and the dielectric layer, and a layer disposed over the interconnect to establish an interface between the conduction material, the barrier material, and the layer. A plate is disposed along a section of the interconnect to interrupt the interface.

Abstract: A teleconferencing environment is provided in which both audio and visual cues are used to identify active participants and presenters. Embodiments provide an artificial environment, configurable by each participant in a teleconference, that directs the attention of a user to an identifier of an active participant or presenter. This direction is provided, in part, by stereo-enhanced audio that is associated with a position of a visual identifier of an active participant or presenter that has been placed on a window of a computer screen. The direction is also provided, in part, by promotion and demotion of attendees between attendee, active participant, and current presenter and automatic placement of an image related to an attendee on the screen in response to such promotion and demotion.

Abstract: An integrated circuit comprises a transistor body control circuit for controlling a body of a bidirectional power transistor. The transistor body control circuit comprises switches connected between a body terminal and a first current terminal, with a control terminal for controlling the current flowing through the switch. The control terminal of the switch is connected to alternating current, AC capacitive voltage divider. The AC capacitive voltage dividers are connected to the control terminals and arranged to control the switches to switch the voltage of the body terminal as a function of the voltage between the first current terminal and the second current terminal. The integrated circuit further comprises a bi-directional power transistor connected to the transistor body control circuit.

Abstract: A semiconductor device including a voltage regulator is disclosed. The voltage regulator may include a multipath amplifier stage, a driver stage coupled to the multipath amplifier stage, a dynamic compensation circuit coupled to the multipath amplifier stage, and a current compensation circuit. The dynamic compensation circuit may be operable to provide a varying level of compensation to the multipath amplifier stage, where the varying level of compensation proportional to a current level associated with the load; and the current compensation circuit may be operable to allow a minimum current level at the driver stage.

Abstract: An integrated circuit package has a first side and an opposite second side. The integrated circuit package comprises: a stack of layers comprising at least a first and second electrically isolating layers, a dielectric material arranged on the stack of layers at the second side for encapsulating the integrated circuit package, a first integrated antenna structure for transmitting and/or receiving a first radio frequency signal, and a first array of electrically conductive vias extending through at least the first electrically isolating layer and the dielectric material. The first integrated antenna structure is arranged between the first and second electrically isolating layers and is surrounded by the electrically conductive vias which are electrically connected to respective first metal patches arranged on the dielectric material at the second side.

Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of the device using a device design, a device model and a simulation scenario; and one or more violation monitor for each violation rule. At least one of the violation monitors comprises a violation information detector and a threshold controller. The violation information detector is arranged to detect one or more violations of the respective violation rule of the one or more violation rules during the executing the simulation of the device and, for each violation, determine information representing the respective violation, wherein the detecting the one or more violations comprises comparing a simulated parameter against a threshold.