Abstract: An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.

Abstract: A method and circuit for a data processing system (200) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (35-38) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.

Abstract: A high density, low power, high performance information system, method and apparatus are described in which an integrated circuit apparatus includes a plurality of deflectable MEMS optical beam waveguides (e.g., 190) at each die edge which are each formed with an optical beam structure (193) which is encapsulated by a waveguide beam structure (194) to extend into a deflection cavity (198) and which is surrounded by a plurality of deflection electrodes (195-197) that are positioned on walls of the deflection cavity (198) to provide two-dimensional deflection control of each deflectable MEMS optical beam waveguide in response to application of one or more deflection voltages to provide optical communications (e.g., 184) between different die.

Abstract: A scheduling module arranged to schedule the transmission of data from a plurality of data sources over a serial communication interface. The scheduling module comprises a register array and is arranged to selectively couple one of the data sources to the serial communication interface based at least partly on a source identifier value stored within a currently selected register within the register array. The scheduling module is further arranged to select a next sequential register within the register array upon receipt of a trigger signal.

Abstract: A device and a method for an amplifier having reduced intermodulation (IM) distortion output products are presented. An amplifier has an output, and at least one of a gate bias input and a drain supply input. The amplifier is configured to receive an input signal and output an amplified signal at the output of the amplified. An input is configured to receive an envelope signal. The input is connected to the at least one of the gate bias input and the drain supply input and the envelope signal is at least partially determined by an attribute of the input signal to the amplifier. A controller is configured to modify at least one of an amplitude and a phase of the envelope signal to reduce a magnitude of an intermodulation distortion product of the amplifier.

Abstract: An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data.

Abstract: A system and method of clocking an integrated circuit (IC) includes determining operating characteristics of the IC. The IC has multiple domains and each domain receives a respective domain clock signal. A skew value is determined for each of the domain clock signals, where each skew value is associated with a respective domain of the IC. The domain clock signals are generated from a reference clock signal and each domain clock signal is skewed from the reference clock according to the respective skew value.

Abstract: An electronic component package that includes a package substrate having an aluminum bond pad formed from an aluminum clad copper structure. The aluminum clad copper structure is attached to a dielectric layer. An electronic component is attached to the substrate and includes a conductive structure electrically coupled to the aluminum bond pad. The aluminum bond pad, the electronic component, and at least a portion of the substrate are encapsulated with an encapsulant.

Abstract: A method and circuit for testing an analog-to-digital converter (ADC) are provided. The method comprises: coupling a single-ended output of an analog signal source to a differential input of an amplifier; coupling a differential output of the amplifier to a differential input of the ADC; alternately providing first and second test signals from the single-ended output of the analog signal source to first and second input terminals of the differential input of the amplifier; amplifying the first and second test signals to generate amplified differential signals at the differential output of the amplifier; providing the amplified differential signals to the differential input of the ADC; and determining if an output of the ADC is as expected. An offset may also be provided to the differential output of the amplifier. The method allows an ADC having a differential input to be tested using a digital-to-analog converter (DAC) having a single-ended output.

Abstract: Forming a transistor transistor includes forming a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. The drain dopant region is formed within the surface region on the drain side. The drift dopant region is formed within the surface region between the drain side boundary and the drain dopant region. The set of electrically conductive shield plates includes a first shield plate overlying the drift dopant region. The shield plate dopant region is formed within the drift dopant region and underlies the set of shield plates.

Abstract: A ternary content addressable memory (TCAM) cell is coupled to a first word line and a first match line and includes a first data storage portion coupled to a first search line, a second data storage portion coupled to a complement of the first search line, and a resistor divider portion including two resistive elements coupled in series with the first and second data storage portions of the first TCAM cell. The first and second data storage portions of the first TCAM cell are coupled to a first supply voltage and include two resistive elements coupled in parallel.

Abstract: A device includes an integrated circuit (IC) carrier for a semiconductor device, and a coating on the IC carrier. In the presence of an electrical field or a magnetic field, the coating includes a first functional group that attracts anions and a second functional group that attracts cations.

Abstract: To securely configure an electronic circuit and provision a product that includes the electronic circuit, a first entity (e.g., a chip manufacturer) embeds one or more secret values into copies of the circuit. A second entity (e.g., an OEM): 1) derives a trust anchor from a code signing public key; 2) embeds the trust anchor in a first circuit copy; 3) causes the first circuit copy to generate a secret key derived from the trust anchor and the embedded secret value(s); 4) signs provisioning code using a code signing private key; and 5) sends the code signing public key, the trust anchor, and the signed provisioning code to a third entity (e.g., a product manufacturer). The third entity embeds the trust anchor in a second circuit copy and causes it to: 1) generate the secret key; 2) verify the signature of the signed provisioning code using the code signing public key; and 3) launch the provisioning code.

Abstract: An integrated circuit (IC) device is provided that includes at least one internal voltage regulator arranged to receive a voltage supply signal at a first input thereof, receive a control signal at a second input thereof, regulate the received voltage supply signal in accordance with the received control signal, and provide a regulated voltage supply signal at an output thereof. The IC device further includes at least one voltage regulation power control module operably coupled to the second input of the at least one internal voltage regulator and arranged to provide the control signal thereto. The voltage regulation power control module is further arranged to receive at least one IC device conditional indication, and generate the control signal for the at least one internal voltage regulator based at least partly on an available thermal power budget for the IC device corresponding to the at least one IC device conditional indication.

Abstract: A BIST circuit is provided for testing the status of power supplies in an integrated circuit in multiple power modes including multiple circuit blocks. The BIST circuit includes a finite state machine (FSM), power monitors and a comparator. The FSM sequentially enables at least two power mode states in a predetermined order. In each power mode state, the FSM outputs power mode signals to enable the power supplies used in the corresponding power mode. Each power monitor is connected to a power input node of one of the circuit blocks, and outputs a monitor signal indicative of the voltage at the corresponding power input node when the corresponding power supply is enabled. The comparator compares each monitor signal with a corresponding reference signal and generates a set of power supply status signals.

Abstract: The present application relates to a method and a processing system for automated managing of the usage of alternative code. Code sections including original code and alternative code are retrieved from a code basis and the retrieved code is analyzed to detect an alternative code section. A condition definition associated with the identified alternative code section is further retrieved and the condition of the retrieved condition definition is evaluated. The identified alternative code section is activated in accordance with the evaluation result.

Abstract: A system method of initializing operation of a semiconductor device including detecting de-assertion of an external reset signal while the semiconductor device in a reset state, monitoring a temperature level of the semiconductor device, and while the temperature level is below a predetermined minimum operating temperature level that allows the semiconductor device to operate at a maximum performance level, keeping the semiconductor device in the reset state and asserting at least one operating parameter on the semiconductor device at an elevated level to generate heat on the semiconductor device, and releasing the reset condition when the temperature level is at least the predetermined minimum operating temperature level. The operating parameter may be clock frequency or supply voltage level or a combination of both. Different elevated clock frequencies and/or different minimum operating temperature levels are contemplated.

Abstract: A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.

Abstract: A level shifter includes a latch having first and second branches, first and second outputs, first and second control switches in series between the respective branches and outputs, and a controller receiving first and second output signals and outputting first and second control signals to the first and second control switches for controlling activation thereof. In an initial state, the first output signal is in the first state, the first control switch is activated, the second output signal is in the second state, and the second control switch is deactivated. In a final state, the first output signal is in the second state, the first control switch is deactivated, the second output signal is in the first state, and the second control switch is activated. The controller changes the first and second control signals only after the first and second output signals reach the respective second and first states.

Abstract: A passive equalizer includes a first resistive element coupled between a first input node and a first output node, a first capacitive element, a first variable resistor, and a first inductive element coupled in series between the first input node and the first output node, a first transistor having a first current electrode coupled to the first output node, and a first current source coupled to the first current electrode of the first transistor.