Abstract: Apparatus and methods are provided for performing a sampling sequence for a plurality of samples. An analog-to-digital conversion module comprises a sampling module, a register, and a sampling control module coupled to the sampling module and the register. The sampling module is configured to convert analog signals into corresponding digital values in response to sampling trigger signals and the register is configured to maintain scan mode criteria for a plurality of samples. The sampling control module is configured to identify a scan mode criterion for a respective sample of the plurality of samples, automatically generate a sampling trigger signal when the scan mode criterion for the respective sample is equal to a first value, and generate the sampling trigger signal in response to a timing trigger signal when the scan mode criterion for the respective sample is equal to a second value.

Abstract: A semiconductor switch arrangement comprises a bipolar transistor and a semiconductor power switch having an input node, an output node and a control node for allowing a current path to be formed between the input node and the output node. The bipolar transistor is coupled between the input node and the control node such that upon receiving an electro-static discharge pulse the bipolar transistor allows a current to flow from the input node to the control node upon a predetermined voltage being exceeded at the input node to allow the control node to cause a current to flow from the input node to the output node. Thus, the bipolar transistor device protects the semiconductor switch device, such as an LDMOS device, against ESD, namely protection against power surges of, say, several amperes in less than 1 usec.

Abstract: A result value, such as a parity value, for a set of corresponding data elements from a plurality of storage devices is determined using a commutative operation. When accessing the set of corresponding data elements from a plurality of storage devices, a dual access can be performed for the storage device accessed last for the set of corresponding data elements so as to also obtain a data element from the last-accessed storage device for the next parity calculation. As a result, the number of storage device accesses can be reduced compared to conventional systems whereby a single access is performed for each storage device to obtain a single data element from the storage device.

Abstract: A network bridge (160) is provided, comprising: a local interface (320) configured to transmit and receive local signals in a local network (305); a bridging interface (325) configured to transmit and receive bridging signals in a bridging network (310); a control circuit (330) configured to pass outgoing local data packets from the local network to the bridging network and to pass incoming bridging payloads from the bridging network to the local network; and an address translation circuit (340) configured to provide the control circuit with address translation data identifying a correspondence between local packet addresses and global packet addresses. The control circuit translates outgoing local addresses to outgoing global addresses (460), and the control circuit translates incoming global addresses to incoming local addresses (560), based on the address translation data.

Abstract: Improved Schottky diodes (20) with reduced leakage current and improved breakdown voltage are provided by building a JFET (56) into the diode, serially located in the anode-cathode current path (32). The gates of the JFET (56) formed by doped regions (38, 40) placed above and below the diode's current path (32) are coupled to the anode (312) of the diode (20), and the current path (32) passes through the channel region (46) of the JFET (56). Operation is automatic so that as the reverse voltage increases, the JFET (56) channel region (46) pinches off, thereby limiting the leakage current and clamping the voltage across the Schottky junction (50) at a level below the Schottky junction (50) breakdown. Increased reverse voltage can be safely applied until the device eventually breaks down elsewhere. The impact on device area and area efficiency is minimal and the device can be built using a standard fabrication process so that it can be easily integrated into complex ICs.

Abstract: A system on a chip includes a processing module, ROM, RAM, and a clocking circuit. The clock circuit is coupled to produce a first clock signal when the SOC is in a low power mode and to produce a second clock signal when the SOC is in a performance mode, where the first clock signal is less accurate than the second clock signal. The clock circuit consumes more power when producing the second clock signal than when producing the first clock signal.

Abstract: A buffering apparatus to process digital communication signals includes a plurality of buffers, a processing unit, and programmed memory. The programmed memory has instructions directing the processing unit to process the digital samples corresponding to a group of symbols to be processed in a plurality of buffers. The digital samples start in a first buffer of the plurality of buffers and end in a second buffer of the plurality of buffers. The digital samples are received at a third buffer of the plurality of buffers during the processing of the digital samples.

Abstract: Methods and corresponding systems for allocating resources in a communications system includes determining feasible sets of subchannels for allocation to a user subject to an allocation constraint. In one approach, a constraint matrix representing constraints for allocating subchannels to users in allocations of selected subchannels is computed, subject to the allocation constraint. Then a vector containing metrics corresponding to allocations of selected subchannels to the communication links is estimated. A binary decision vector representing an allocation of the subchannels to the users is computed using binary integer processing. In another approach a greedy heuristic allocation is used. The allocation constraint can be a restriction limiting multiple subchannels allocated to a user to be adjacent to one another. The metrics can be weighted capacities of allocations of selected subchannels to the users.

Abstract: A radio frequency receiver (102) includes at least one amplifier (108, 114 and 122) for amplifying a signal received by the radio frequency receiver, an automatic gain control system (158) for controlling a gain of the at least one amplifier, and a direct current offset correction filter (142) for reducing any direct current component of the signal amplified by the at least one amplifier. The direct current offset correction filter has a bandwidth that is dynamically controlled by a change in the gain of the at least one amplifier. The radio frequency receiver also includes a digital automatic gain control unit (150) having a bandwidth that is dynamically controlled by the change in the gain of the at least one amplifier.

Abstract: A technique of operating a wireless communication device includes selecting, from a primary sequence group that includes respective primary sequences, one of the respective primary sequences as a first portion of a cell identification (ID). In this case, the respective primary sequences are each associated with respective secondary sequence subgroups included in a secondary sequence group. Each of the respective secondary sequence subgroups include secondary sequences. One of the secondary sequences is selected (from one of the respective secondary sequence subgroups that is associated with the selected one of the respective primary sequences) for a second portion of the cell ID. At least some of the secondary sequences are only included in one of the respective secondary sequence subgroups. The first portion of the cell ID is encoded on a first downlink waveform that is to be transmitted and the second portion of the cell ID is encoded on a second downlink waveform that is to be transmitted.

Abstract: A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer.

Abstract: An electrostatic discharge (ESD) protection device (41, 51, 61, 71, 81) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (41, 41?, 41?; 71, 71?, 71?), each stage (41, 41?, 41?; 71, 71?, 71?) comprising first (T1, T1?, T1?, etc.) and second transistors (T2, T2?, T2?? etc.) having a common collector (52, 52?, 52?) and first (26, 26?, 26?) and second (36, 36?, 36?) emitters providing terminals (32, 42; 32?, 42?; 32?, 42?) of each clamp stage (41, 41?, 41?; 71, 71?, 71. A first emitter (25) of the first stage (41, 71) couples to the common terminal (23) and a second emitter (42?) of the last stage (41?, 71?) couples to the I/O terminals (22). Zener diode triggers are not used. Integrated external ESD trigger resistors (29, 29?, 29?; 39, 39?, 39?) (e.g.

Abstract: A semiconductor device includes a substrate (20), a source region (58) formed over the substrate, a drain region (62) formed over the substrate, a first gate electrode (36) over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode (38) over the substrate adjacent to the drain region and between the source and drain regions.

Abstract: A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.

Abstract: A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.

Abstract: A method used in an adaptive survivor based channel equalizer, the method comprises selecting at a decision time a survivor in a Viterbi trellis and a corresponding equalizer, adaptively updating at the decision time the corresponding equalizer to define a new corresponding equalizer for use at a next decision time, retrieving the new corresponding equalizer as defined at an earlier decision time, and using the new corresponding equalizer as defined at an earlier decision time as an equalizer for other survivors in the Viterbi trellis at the next decision time. A corresponding adaptive survivor based channel equalizer includes a fixed pre-filter configured to provide a pre-filtered signal to a reduced state sequence estimator (RSSE) which is configured for providing recovered symbols. A coefficient adaptor is coupled to the RSSE and configured to essentially perform the method.

Abstract: A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.

Abstract: Embodiments of a magnetoresistive random access memory (MRAM) array include multiple transistors having source and drain regions, and multiple substantially planar MRAM bits. The MRAM bits have upper and lower electrodes and intervening magnetics layers. The lower electrodes of at least some of the MRAM bits are formed substantially directly on at least some of the source or drain regions without an intervening via. Embodiments of an MRAM array also include a first conductive interconnect layer above and in electrical contact with the upper electrodes of at least some of the MRAM bits, with no metal layers intervening between the upper electrodes and the first conductive interconnect layer.

Abstract: A data processing system may include a first data path and a second data path. A set of components may include a system component and a partner component, each having a communication interface for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non-synchronized mode configuration. The configuration control system may include a first path selector module connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module connecting the communication interface of the partner component to the first data path and the second data path.

Abstract: A DAC unit, connected to a current supply transistor, includes first control transistors connected in parallel to each other, with each being connected in series to the current supply transistor. The first control transistors drive currents at different current values in response to a bias voltage. The DAC unit also includes second control transistors connected in parallel to each other, with each being connected in series to the current supply transistor. Each second control transistor drives the current having the same current value as one of the first control transistors in response to the single bias voltage. The first and second control transistors driving the currents having the same current value operate in a complementary manner based on part of a digital code. The DAC unit generates an output current by selectively combining at least one of the currents driven by the first control transistors.