Abstract: An amplifying circuit has an offset calibration mode and a normal mode. The amplifying circuit includes an amplifier having a non-inverting input and an inverting input for receiving, during the normal mode, a first input signal and a second input signal and an output for providing a high speed output signal, wherein the first input signal is a reference voltage or a high speed signal and the second input signal is a high speed signal. The amplifying circuit further includes a first transmission gate and a second transmission gate coupled in series between the non-inverting input and an inverting input that are enabled during the offset calibration mode. A benefit of this approach is that capacitance between the inverting and non-inverting inputs is reduced by the first and second transmission gates being in series. There is further benefit in reducing this capacitance by having each transmission gate receive an enable signal from a different source.

Abstract: A method, computer program product, and data processing system for combining results regarding test sequences' coverage of events in testing a plurality of related semiconductor designs are disclosed. Test patterns are randomly generated by one or more “frontend” computers. Results from applying these patterns to the designs under test are transmitted to a “backend” computer in the form of an ordered dictionary of events and bitmap and/or countmap data structures. The backend computer combines results from each test sequence in a cumulative fashion to measure the overall coverage of the set of test sequences over the plurality of designs.

Abstract: A method and apparatus are provided for providing improved radio frequency (RF) receiver signal correction. For RF receiver circuitry (106) having receive path and a warmup period associated therewith and including at least one analog baseband gain control stage (218) having a gain associated therewith, the method includes the step of performing a DC correction calculation operation during the warmup period to derive a DC correction value having a first component and a second component for each of the at least one gain control stage (218). The DC correction calculation step includes the steps of performing a first closed loop correction (460) of a baseband path to derive the first component of the DC correction value and performing a second closed loop correction (462) of the receive path as a function of the (218) gain during the warmup period to derive the second component of the DC correction value.

Abstract: A comparator circuit (300) has a first field effect transistor (FET) (307) with a supply voltage (301) connection and a diode connected FET (303) connected in series to form the first circuit leg of the comparator (300). A second diode connected FET (309) and a second FET (305) in series form the second circuit leg. The first FET (307) and said second FET (305) are approximately equal sized FETs. Another embodiment is an integrated circuit (401) with two n-channel FETs. A first diode connected FET (303) is connected to the first n-channel FET (307) in series to form the first circuit leg of a comparator (300) and a second diode connected FET (309) is connected to a second n-channel FET (305) in series to form the second circuit leg of the comparator. The two n-channel FETs that form the differential pair are approximately equal in size. The trip point is high with respect to the supply voltage.

Abstract: A method for transferring a predetermined pattern onto a flat support performed by direct writing by means of a particle beam comprises at least: deposition of a photoresist layer on a free surface of the support, application of the beam on exposed areas of the photoresist layer, performing correction by modulation of exposure doses received by each exposed area, developing of the photoresist layer so as to form said pattern. Correction further comprises determination of a substitution pattern (11) comprising at least one subresolution feature and use of the substitution pattern (11) for determining the areas to be exposed when the electron beam is applied. In addition, modulation takes account of the density of the substitution pattern (11) near to each exposed area.

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form a top electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).

Abstract: A circuit includes a clock conditioning circuit which receives an encoded clock signal, and provides first and second conditioned clock signals in response. The clock conditioning circuit adjusts a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The circuit includes a modulator which receives the first and second conditioned clock signals.

Abstract: A decoder includes a sample rate conversion module, a decoding module, and an error sensing module. The sample rate conversion module is operably coupled to convert, based on an error feedback signal, rate of an encoded signal from a first rate to a second rate to produce a rate adjusted encoded signal. The decoding module is operably coupled to decode the rate adjusted encoded signal to produce a decoded signal. The error sensing module is operably coupled to produce the error feedback signal based on the decoded signal.

Abstract: A voltage-controlled oscillator circuit comprises an output terminal for providing an oscillatory output signal thereat, a first inductor, a varactor, and a negative-resistance element. The varactor's capacitance is a function of a tuning potential applied at a first terminal of the varactor. A bias branch is present for coupling a second terminal of the varactor to a bias potential. The bias branch comprises a second inductor or a transmission line. The bias branch may comprise a transmission line the length of which is one quarter wavelength associated with the resonance frequency of the voltage-controlled oscillator circuit. A radar system including a VCO circuit is further disclosed.

Abstract: Latch-up of CMOS devices (20, 20?) is improved by using a structure (40, 40?, 80) having electrically coupled but floating doped regions (64, 64?; 65, 65?) between the N-channel (44) and P-channel (45) devices. The doped regions (64, 64?; 65, 65?) desirably lie substantially parallel to the source-drain regions (422, 423; 432, 433) of the devices (44, 45) between the Pwell (42) and Nwell (43) regions in which the source-drain regions (422, 423; 432, 433) are located. A first (“N BAR”) doped region (64, 64?) forms a PN junction (512) with the Pwell (42), spaced apart from a source/drain region (423) in the Pwell (42), and a second (“P BAR”) doped region (55, 55?) forms a PN junction (513) with the Nwell (43), spaced apart from a source/drain region (433) in the Nwell (43). A further NP junction (511) lies between the N BAR (64) and P BAR (65) regions.

Abstract: Embodiments of the systems and methods utilize application contexts for extending virtual machines in a resource-constrained device to allow virtual machines to at least exercise scheduling control over platform independent applications and platform dependent native applications. Application contexts can be assigned to each application in the system. An application is represented by one or more data structures and functions. In one embodiment, an “application context” includes an interface to a virtual machine and a container for an execution environment of the application. The interface represents a mapping of services to an execution environment. The application context can isolate control over the execution of the application from the execution environment, thus, allowing the virtual machine to control execution of the application and allowing the application to be executed in a native environment, a virtual machine environment, or any other execution environment.

Abstract: Embodiments of semiconductor structures are provided for a semiconductor device employing a superjunction structure. The device includes interleaved regions of first and second semiconductor materials of, respectively, first and second conductivity types and first and second mobilities. The second conductivity type is opposite the first conductivity type and the second mobility exceeds the first mobility for a first carrier type. The first and second semiconductor materials are separated by substantially parallel PN junctions and form a superjunction structure. The device also includes electrical contacts coupled to the first and second materials so that, in response to applied signals, a principal current of the first carrier type flows through the second material.

Abstract: Signal edge alignment embodiments include multiple delay stages connected in series. Each delay stage includes a delay line, an interface circuit, and a tap selection circuit. The delay line applies fixed-width delays to an input signal to produce delayed versions of the input signal at a plurality of taps. The interface circuit, which is characterized by an inherent interface circuit delay, passes one of the delayed versions to an interface circuit output in response to a control signal. The tap selection circuit determines a finally-identified tap of the plurality of taps by determining an initially-identified tap at which a delayed version of the input signal most closely has a desired alignment with the input signal, and by identifying the finally-identified tap in the control signal as a tap that occurs earlier in the delay line than the initially-identified tap. This compensates for the inherent delay of the delay stage.

Abstract: Techniques have been developed to facilitate concurrent evaluation of hash rule entries in ways that allow an implementation to maintain a deterministic resultant hash irrespective of variations in the allocation of particular rules to particular storage banks or evaluation logic, such as may occur with rule set revisions. Similarly, uniform deterministic hash results can be assured even across a range of implementations that support greater or lesser levels of concurrent rule evaluations.

Abstract: A processing module including an interpolator, a demodulator, and a tracking module. The interpolator applies a feedback signal to a first digitized signal having a first data rate to produce a second digitized signal having a second data rate. The demodulator processes the second digitized signal to produce a digital composite signal having a timing component. The tracking module mixes the digital composite signal with a reference signal and produces the feedback signal. The tracking module may include a mixer, a filter, a comparator, a loop filter and a quantizer. The mixer and filter mixes an input signal with a reference signal to provide a filtered timing error signal. The comparator compares the timing error signal with a reference signal and produces an offset signal. The loop filter processes the offset signal to produce a filtered offset. The quantizer processes the filtered offset to produce the feedback signal.

Abstract: A polishing pad can include a first layer and a second layer. The first layer can have a first polishing surface and a first opening. The second layer can have an attaching surface and a second opening substantially contiguous with the first opening. The polishing pad can further include, a pad window lying within the first opening. The pad window can include a second polishing surface. When the pad would be attached to a platen, the first and second polishing surfaces can lie along a same plane, and an opposing surface of the pad window can abut an exterior surface of a platen window. In another aspect, a polishing apparatus can include an exterior surface of a platen window abutting the polishing pad. In still another aspect, a process of polishing can include polishing a workpiece such that the pad window contacts the workpiece and the platen window simultaneously.

Abstract: A package assembly 200 includes a semiconductor die (e.g., an RF power amplifier) 208 fixed within the cavity of a conductive leadframe 204 using a thermally and electrically-conductive adhesive material 209. The semiconductor die 209 has a first side and a second side, wherein the first side includes at least one active area, and the second side includes at least one contact region. The conductive leadframe (e.g., a copper leadframe) 204 has two planar surfaces and a cavity formed therein. The adhesive material 209 is configured to couple the semiconductor die 208 within the cavity of the conductive leadframe 204 such that the first side of the semiconductor die is substantially coplanar with the first surface of the conductive leadframe.

Abstract: A system and method provides branch target buffer (BTB) allocation. When a branch instruction is received, a branch target address that corresponds to the branch instruction is determined. A determination is made whether the branch target address is presently stored in a branch target buffer (BTB). When the branch target address is not presently stored in the branch target buffer, an entry in the branch target buffer is identified to receive the branch target address. A value in a field within the identified entry in the branch target buffer, such as a postponement flag (PF), is used to selectively override a replacement decision defined by predetermined branch target buffer allocation criteria. In one form, if a branch is taken, the identified entry is replaced with the branch target address in response to determining that the value in the field within the identified entry has a predetermined value.

Abstract: A method and system for executing a software application having a binary size that is larger than an available memory space in an embedded system from which the software application will execute. The software application is split into one or more initialization sequences and a main code sequence. The method includes loading (302) each initialization sequence of the one or more initialization sequences in the memory space prior to its execution, and executing (304) each initialization sequence of the one or more initialization sequences out of the memory space. Further, the method includes loading (306) the main code sequence in the memory space after the execution of the one or more initialization codes and then executing (308) the main code sequence out of the memory space.

Abstract: A method (20, 104) for processing a panel (26, 128) during semiconductor device (52) fabrication entails forming grooves (72, 142) in a surface (34, 132) of the panel (26, 128) coincident with a dicing pattern (54) for the panel (26, 128). The grooves (72, 142) extend partially through the panel (26, 128) so that the panel (26, 128) remains intact. The grooves (72, 142) relieve stress in the panel (26, 128) to reduce panel (26, 128) warpage, thus enabling the panel (26, 128) to be reliably held on a support structure (88, 98, 138) via vacuum when undergoing further processing, such as solder printing (86). The method (20, 104) further entails, dicing (96, 152) through the panel (26, 128) from the surface (34, 132) in accordance with the dicing pattern (54) while the panel (26, 128) is mounted on the support structure (98, 138) to singularize the semiconductor devices (52).