Abstract: A method of forming a power semiconductor device comprises forming a first semiconductor layer of a first conductivity type extending across the power semiconductor device; forming an epitaxial layer of the first conductivity type over the first semiconductor layer, the epitaxial layer having a doping concentration that increases from a first surface of the epitaxial layer towards the first semiconductor layer; forming a body region of a second conductivity type in the epitaxial layer extending from the first surface of the epitaxial layer into the epitaxial layer, wherein a junction between the body region and the epitaxial layer is at or substantially adjacent to a region of the epitaxial layer having a maximum doping concentration; and forming a gate region such that the gate region is adjacent at least a portion of the body region. In operation of the semiconductor device, the portion of the body region adjacent the gate region functions as a channel region of the semiconductor device.

Abstract: A data processor and method for processing position-related input data from a rotational machine whose angular speed is variable and providing output data at an output data rate. The processor comprises a time-based over-sampler for over-sampling the input data at an over-sampling rate greater than the output data rate, and a down-sampler for extracting samples of over-sampled data from the over-sampler at the output data rate so as to provide the output data. The down-sampler is responsive to an angular timing signal related to an angular position of the machine for selecting the samples of over-sampled data to extract based on the angular position. Application to a rotational machine whose angular speed is variable, in particular to an internal combustion engine to control engine operating parameters as a function of cylinder pressure.

Abstract: A technique of operating a wireless communication device in a multiple-input multiple-output wireless communication system includes receiving, at a first wireless communication device, recommended precoder information from a second wireless communication device, which is associated with a recommended precoder. A precoded signal is then formed at the first wireless communication device based on the recommended precoder or an alternate precoder. The first wireless communication device, which is configured to not provide an indication of whether the recommended precoder or the alternate precoder was utilized to form the precoded signal, then transmits the precoded signal.

Abstract: A semiconductor package substrate (11) has an array of package sites (13, 14, 16, and 21) that are substantially identical. The entire array of package sites (13, 14, 16, and 21) is covered by an encapsulant (19). The individual package sites (13, 14, 16, and 21) are singulated by sawing through the encapsulant (19) and the underlying semiconductor package substrate (11).

Abstract: Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.

Abstract: Embodiments include methods, apparatus, and electronic systems adapted to perform adaptive pre-distortion. Embodiments include combining an input sample with a gain value to generate a pre-distorted data sample, where the gain value is a function of at least one gain entry stored within a gain lookup table. An amplified analog signal is generated from the pre-distorted data sample, and a feedback sample is also generated, which corresponds to an antenna output signal. The antenna output signal includes the amplified analog signal. A difference indicator is generated to reflect a difference between the input sample and the feedback sample, and at least one updated gain value is generated based on a comparison between the difference indicator and at least one previous difference indicator. At least one gain entry within the gain lookup table is updated with the at least one updated gain value.

Abstract: A codec includes an output module for converting a digital input signal into an analog output signal. A controller module monitors a plurality of status conditions and asserts a mute signal for engaging an output mute switch based on a plurality of disconnect rules.

Abstract: An electronic device can be used with a system, such as an ignition system, that operates a relatively high voltage. The device can include a signal clamping control module that can include a signal reference module and a feedback control module. The signal reference module is operable to provide a reference signal to the feedback control module. The feedback control can be configured to receive a scaled signal from a signal scaling module, wherein the scaled signal is representative of a signal at a current carrying electrode of a power transistor. Based on the comparison of the reference signal to the scaled signal, the measurement module provides one or more signals to a control signal drive module. The feedback control module provides a control electrode signal to a control electrode of the power transistor.

Abstract: A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region. The method further includes forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source.

Abstract: A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.

Abstract: A double-balanced sinusoidal mixing phase interpolator circuit comprises: a double-balanced gain stage having a first input for receiving a first phasor clock, a second input for receiving a second phasor clock, and a phase interpolator (PI) output, wherein the double-balance gain stage includes (i) a first gain stage having a positive input side and a negative input side for the first phasor clock and (ii) a second gain stage having a positive input side and a negative input side for the second phasor clock; and a sinusoidal digital-to-analog (DAC) stage coupled to the double-balanced gain stage and configured to implement sinusoidal weighting of positive and negative sides of differential DAC current for the first phasor clock and positive and negative sides of differential DAC current for the second phasor clock, wherein the sinusoidal weighting provides uniformly spaced phase steps in the phase interpolator (PI) output.

Abstract: An automatic gain control (AGC) system for a receiver and corresponding method facilitate AGC in a receiver. The automatic gain control system includes an on-channel signal detector 123 configured to provide an on-channel signal level indication corresponding to a narrow band on-channel signal and a wideband signal detector 121 configured to provide a wideband signal level indication corresponding to a wideband signal, where the wideband signal includes the narrow band on-channel signal. Further included is a controller 149 that is coupled to the wideband signal level indication and the on-channel signal level indication and that is configured to provide a gain control signal corresponding to the wideband signal level and one or more of a plurality of states of the receiver.

Abstract: By providing a novel bipolar device design implementation, a standard CMOS process (105-109) can be used unchanged to fabricate useful bipolar transistors (80) and other bipolar devices having adjustable properties by partially blocking the P or N well doping (25) used for the transistor base (581). This provides a hump-shaped base (583, 584) region with an adjustable base width (79), thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process (101-104) alone. By further partially blocking the source/drain doping step (107) used to form the emitter (74) of the bipolar transistor (80), the emitter shape and effective base width (79) can be further varied to provide additional control over the bipolar device (80) properties. The embodiments thus include prescribed modifications to the masks (57, 62, 72, 46) associated with the bipolar device (80) that are configured to obtain desired device properties.

Abstract: A method for controlling multiple DMA tasks, the method includes receiving multiple DMA task requests; the method is characterized by defining multiple buffer descriptors for each of a plurality of DMA channel; wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; selecting a DMA task request out of the multiple DMA task requests; executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and jumping to the stage of selecting.

Abstract: A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.

Abstract: A device and a method for evaluating ESD protection capabilities of an integrated circuit, the method includes: connecting multiple test probe to multiple integrated circuit testing points. The method is characterized by repeating the stages of: (i) charging a discharge capacitor to an ESD protection circuit triggering voltage level; (ii) connecting the discharge capacitor to the integrated circuit during a testing period such as to cause the discharge capacitor to interact with the integrated circuit; (iii) measuring at least one signal of the integrated circuit, during at least a portion of the testing period; and (iv) determining at least one ESD protection characteristic of the integrated circuit in response to the at least one signal.

Abstract: Techniques for performing user-configurable traffic management functions on streams of packets. The functions include multicasting, discard, scheduling, including shaping, and segmentation and reassembly. In the techniques, the functions are not performed directly on the packets of the stream, but instead on descriptors that represent stored packets. Output of descriptors from all traffic queues, including discard traffic queues, is scheduled. Scheduling is done using a hierarchy of schedulers. The form of the hierarchy and the scheduling algorithms used by the schedulers in the hierarchy are both user configurable. As disclosed, the techniques are implemented in a traffic management coprocessor integrated circuit. The traffic manager coprocessor is used with a digital communications processor integrated circuit that performs switching functions. The buffers for the packets are in the digital communications processor.

Abstract: A voltage regulator includes a first multi-gate transistor, a differential stage, a second stage having a second multi-gate transistor, and a pass transistor to apply an output voltage and output current to a device load. Based on a feedback voltage associated with the output voltage, the differential stage modulates a bias voltage applied to a control electrode of the pass transistor. A first gate of the second multi-gate transistor generates a nominal bias current for the pass transistor, and the second gate adjusts the bias voltage based on an output of the differential stage so that transients in the regulator output voltage resulting from sudden changes in current drawn by the device load are reduced.

Abstract: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

Abstract: A semiconductor device comprises at least one switching element. The at least one switching element comprises a first channel terminal, a second channel terminal and a switching terminal, the switching element being arranged such that an impedance of the switching element between the first and second channel terminals is dependant upon a voltage across the switching terminal and the first channel terminal. The semiconductor device further comprises a resistance element operably coupled between the first channel terminal of the at least one switching element and a reference node, and a clamping structure operably coupled between the switching terminal of the switching element and the reference node.