Abstract: A GMSK receiver with interference cancellation includes a linear equalizer configured to be coupled to a received signal from a first antenna and to provide first soft bits, an adaptive estimator, e.g., adaptive MLSE coupled to the first soft bits and configured to provide second soft bits; a quality assessor coupled to the first soft bits and configured to provide a quality indication; and a switching function coupled to the linear equalizer and the adaptive MLSE and controlled in accordance with the quality indication to provide output soft bits corresponding to at least one of the first soft bits and the second soft bits. The GMSK receiver can be extended to multiple antennas and corresponding methods for interference cancellation in a GMSK signal are discussed.

Abstract: A phase-locked loop (PLL) system generates an oscillator signal based on an input reference signal. A calibration circuit generates a calibration current, and a voltage-to-current converter converts a control voltage into a first current. A current-controlled oscillator generates the oscillator signal based on the first current and the calibration current. A charge pump circuit, which is connected to a phase detector, the voltage-to-current converter, and the calibration circuit, generates a charge pump current based on the first current and the calibration current. The charge pump current is used to generate the control voltage based on an error signal.

Abstract: A method of processing block-based image information including up sample filtering pixels located along boundaries of image blocks using a first filter strength and up sample filtering at least a portion of the pixels that are not located along boundaries of the image blocks using a second filter strength. The method may alternatively include up sample filtering pixels located along boundaries of image blocks and image sub-blocks using the first filter strength. An up sample filter system which includes a first up sample filter which filters pixels located along boundaries of the image blocks using a first filter strength and a second up sample filter which filters pixels that are not located along boundaries of the image blocks using a second filter strength.

Abstract: A charge pump system (100) includes a charge pump (102), and a regulator (101) that includes a clock generator (120) for providing a clock signal, a control logic (130) coupled to the clock generator, and a comparator (140) coupled to an output of the charge pump. The comparator includes a plurality of interleaved latches (211, 212, 213 and 214) driven by a single differential (203) stage that compares the output voltage and a reference voltage. The control logic provides timing signals to cause each latch to perform a latch action at different points in time within each period of the clock signal, each point in time equally spaced apart. An output from each latch is coupled to an output stage (205). An output signal from the output stage regulates an output voltage from the charge pump. In one embodiment, the charge pump is coupled to a flash memory (190).

Abstract: A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial function. The processing logic is further arranged to: divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions; derive inverse functions for the set of linear functions defining the subgroups; and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.

Abstract: A display controller includes a controller input connectable to receive first image data representing a non-safety relevant part of an image to be displayed on a display and to receive second image data representing a safety relevant part of the image. A merging unit is connected to the controller input, for composing the image from the first image data and second image data. A controller output is connectable to the display, for outputting display data representing the image. An image monitor is connected to the controller output, for comparing a part of the image corresponding to the safety relevant part with an reference for the part.

Abstract: A method for patterning a substrate is provided, which comprises (a) providing a substrate; (b) applying a first layer comprising a first photo resist to the substrate; (c) applying a second layer comprising a second photo resist over the first layer; (d) patterning the second layer; and (e) inspecting the patterned second layer with an inspection tool; wherein at least one of the first and second layers comprises a contrasting agent which increases the contrast between the first and second layers to the inspection tool.

Abstract: A control loop has a control slope associated therewith. The control loop is provided to control a unit under control. A method of regulating the control slope comprises the step of measuring the control slope of the control loop and modifying a parameter associated with the unit under control in order to maintain the control slope within a desired range. Lock of the control loop is therefore maintained.

Abstract: An integrated circuit having a memory and a method for operating the memory are provided. The method for operating the memory comprises: accessing a first portion of the memory, the first portion having a first access margin; detecting an error in the first portion of the memory; changing the first access margin to a second access margin, the second access margin being different than the first access margin; determining that the error is corrected with the first portion having the second access margin; and storing an access assist bit in a first storage element, the access assist bit corresponding to the first portion, wherein the assist bit, when set, indicates that subsequent accesses to the first portion are accomplished at the second access margin.

Abstract: A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.

Abstract: A voltage circuit and method charges a circuit node to a first predetermined voltage. The first predetermined voltage charged onto the circuit node is used for a first predetermined function during a first time period. A portion of charge from the circuit node is removed to circuitry coupled to the circuit node. The portion of the charge is reused during a second time period subsequent to the first time period. In one form a voltage generator has diode configurable transistors for passing current in only one direction depending upon whether the circuit node is being charged or discharged. In another form a switch couples the circuit node between a reference terminal and another circuit for charge reuse. Reuse of charge permits increased power savings.

Abstract: A method includes forming a silicon nitride layer and patterning it to form a first opening and a second opening separated by a first portion of silicon nitride. Gate material is deposited in the first and second openings to form first and second select gate structures in the first and second openings. Second and third portions of silicon nitride layer are removed adjacent to the first and second gate structures, respectively. A charge storage layer is formed over the semiconductor device after removing the second and third portions. First and second sidewall spacers of gate material are formed on the charge storage layer and adjacent to the first and second gate structures. The charge storage layer is etched using the first and second sidewall spacers as masks. The first portion is removed. A drain region is formed in the semiconductor layer between the first and second gate structures.

Abstract: A method for making a semiconductor device is disclosed. In accordance with the method, a semiconductor structure is provided which includes (a) a substrate (203), (b) first and second gate electrodes (219) disposed over the substrate, each of the first and second gate electrodes having first and second sidewalls, and (c) first (223) and second (225) sets of spacer structures disposed adjacent to the first and second gate electrodes, respectively. A first layer of photoresist (231) is then disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered, after which the first set of spacer structures is partially etched.

Abstract: A method of converting a plurality of input signals on first and second converters, such that the first and second converters are both used when the plurality of signals comprises two signals, characterised in that said method comprises: selecting more than two input signals; determining the type of each selected signal; combining any signals having the same type to form a combined signal; converting one type of signal with the first converter; converting a second type of signal with the second converter wherein the first or second type signals is a combined signal.

Abstract: A method and apparatus are described for fabricating an exposed backside pressure sensor (30) which protects interior electrical components (37) formed on a topside surface of a pressure sensor transducer die (31) from corrosive particles using a protective gel layer (38) and molding compound (39), but which vents a piezoresistive transducer sensor diaphragm (33) formed on a backside of the pressure sensor transducer die (31) through a vent hole (42) formed in an exposed die flag (36), enabling the sensor diaphragm (33) to directly sense pressure variations without the influence of a protective gel.

Abstract: A control generator is provided, comprising: a summer configured to add a ramping phase adjustment signal and a basic phase adjustment signal to generate a combined phase adjustment signal based on the combined phase adjustment signal; a look-up table configured to generate first through Nth digital phase and frequency adjustment signals; and first through Nth digital to analog converters configured to convert the first through Nth digital phase and frequency adjustment signals to first through Nth analog phase and frequency adjustment signals in accordance with first through Nth clock signals, respectively. wherein N is an integer greater than 1.

Abstract: A voltage supply circuitry is capable of coupling to wired audio headset circuitry and configurable to operate in a first mode, wherein the voltage supply circuitry provides a voltage supply to the wired audio headset functionality circuitry. The voltage supply circuitry is further capable of coupling to visual indication circuitry and further configurable to operate in a second mode, wherein the voltage supply circuitry provides a voltage supply to the visual indication circuitry.

Abstract: A method and apparatus for control of an alternating current electric motor with field weakening, including setting a required operating point for a motor field voltage component as a function of a difference between actual and required motor field current components, and setting a required operating point for a motor torque voltage component as a function of a difference between actual and required motor torque current components. The method also includes setting a field weakening constituent for the required operating point for the motor field voltage component as a function of a difference between a required operating point and an available value of the motor torque voltage component and as a function of a difference between actual and required motor torque current components.

Abstract: A MEMS device (20) with stress isolation includes elements (28, 30, 32) formed in a first structural layer (24) and elements (68, 70) formed in a second structural layer (26), with the layer (26) being spaced apart from the first structural layer (24). Fabrication methodology (80) entails forming (92, 94, 104) junctions (72, 74) between the layers (24, 26). The junctions (72, 74) connect corresponding elements (30, 32) of the first layer (24) with elements (68, 70) of the second layer (26). The fabrication methodology (80) further entails releasing the structural layers (24, 26) from an underlying substrate (22) so that all of the elements (30, 32, 68, 70) are suspended above the substrate (22) of the MEMS device (20), wherein attachment of the elements (30, 32, 68, 70) with the substrate (22) occurs only at a central area (46) of the substrate (22).

Abstract: An amplifying circuit has an offset calibration mode and a normal mode. The amplifying circuit includes an amplifier having a non-inverting input and an inverting input for receiving, during the normal mode, a first input signal and a second input signal and an output for providing a high speed output signal, wherein the first input signal is a reference voltage or a high speed signal and the second input signal is a high speed signal. The amplifying circuit further includes a first transmission gate and a second transmission gate coupled in series between the non-inverting input and an inverting input that are enabled during the offset calibration mode. A benefit of this approach is that capacitance between the inverting and non-inverting inputs is reduced by the first and second transmission gates being in series. There is further benefit in reducing this capacitance by having each transmission gate receive an enable signal from a different source.