Abstract: An analog-to-digital converter (ADC) implements non-uniform conversion accuracy so as to allow for high conversion accuracy for a select narrower input range while also accommodating a wider overall input range and requiring fewer conversion bits compared to conventional ADCs. The ADC includes an ADC core that receives an input signal and outputs a first digital value having a first number of bits, the first digital value based on the input signal and an accuracy configuration of the ADC core. The ADC also includes an encoder to generate a second digital value have a second number of bits, greater than the first number of bits, based on the first digital value and the accuracy configuration of the ADC core. The ADC further includes an accuracy controller to adjust the accuracy configuration of the ADC core based on a relationship between the first digital value and at least one threshold.

Abstract: A device for evaluating connectivity between a video driver and a display, the device comprises a first video driver, a first output connector, a first terminating resistance; wherein the device is characterized by comprising a first comparison unit; wherein the first video driver has an output port that is coupled to the first output connector, to the first terminating resistance and to the first comparison unit; wherein the first output connector is configured to be coupled via a first cable to a first input of the display; wherein the first comparison unit is adapted to perform comparisons between a voltage level on the first terminating resistance to multiple thresholds and to determine whether a display first input impedance is substantially equal to the first terminating resistance, whether the display first input impedance is substantially lower then the first terminating resistance, or whether the first video driver is disconnected from the display; wherein the comparisons are executed during a pixel

Abstract: A clock signal generating arrangement for a communication device generates a system clock signal at an output for use as a timing reference. The clock signal generating arrangement comprises a reference clock generator for generating a reference clock signal, a main clock generator for generating a main clock signal having a greater accuracy than the reference clock signal, a clock adjust circuit coupled to the reference clock generator for generating a compensated reference clock signal to compensate for error in the reference clock signal and a clock signal selector coupled to the reference clock generator the main clock generator and the clock adjust circuit.

Abstract: A branch target buffer (BTB) receives, from a processor, a current fetch group address which corresponds to a current fetch group including a plurality of instructions. In response to the current fetch group address resulting in a group hit in the BTB, the BTB provides to the processor a branch target address corresponding to a branch instruction within the current fetch group which is indicated by a control field as valid and predicted taken. The BTB generates the branch target address using an unshared lower order target portion, corresponding to the branch instruction and located within the entry of the BTB which caused the group hit, and one of a shared higher order target portion located within the entry of the BTB which caused the group hit or a higher order portion of the current fetch group address based on a value of the control field.

Abstract: A method includes forming a first opening in a top surface of a semiconductor substrate, performing an implant into the top surface to form a doped region, epitaxially growing a semiconductor layer in the first opening along a bottom of the first opening and along sidewalls of the first opening, wherein the epitaxially growing comprises in-situ doping the semiconductor layer, filling the first opening with a dielectric material, forming a second opening in the dielectric material, wherein a bottom of the second opening exposes the epitaxially grown semiconductor layer and sidewalls of the second opening expose the dielectric material; and filling the second opening with a semiconductor material, wherein the semiconductor material comprises a top electrode and a bottom electrode. The bottom electrode is in electrical contact with the semiconductor layer which is in electrical contact with the doped region. The doped region is laterally adjacent the semiconductor material.

Abstract: A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.

Abstract: A method of locating a defect of a failed semiconductor device which includes applying a test pattern to the failed semiconductor device and providing failed semiconductor device test responses as a pass signature, applying radiation to each of multiple locations of circuitry of a correlation semiconductor device with sufficient energy to induce a fault in the circuitry, applying the test pattern to the correlation semiconductor device while the radiation is applied to the location and comparing correlation semiconductor device test responses with the pass signature for each location, and determining a defect location of the failed semiconductor device in which correlation semiconductor device test responses at least nearly match the pass signature. The radiation may be a laser beam. The method may include determining an exact match or a near match based on a high correlation result. Asynchronous scanning may be used to provide timing information.

Abstract: A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region (18) is formed over a substrate that is bi-axially stressed. Source (30) and drain (32) regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axially stress are both compressive for P-channel transistors and tensile for N-channel transistors. Both transistor types can be included on the same integrated circuit.

Abstract: A wireless communication method comprises selecting a cause of a disruption from two or more potential causes of disruptions by associating at least one characteristic of a communication with a device with the selected cause of a disruption and changing a data rate for the communication from an existing data rate to a new data rate based upon the at least one characteristic of the communication.

Abstract: Components of a memory controller are calibrated in a select sequence to compensate for variances in skew and signal level variations. The offset bias of the receiver of the I/O cell and the termination resistance of the I/O cell are calibrated. The duty cycles of the transmit path and receive path associated with the I/O cell can be calibrated using the calibrated receiver. In one aspect, the driver of the I/O cell can be calibrated prior to calibrating the receiver. Performing the calibration processes of the memory controller in one of the particular sequences described herein improves the timing budgets for the signaling conducted by the memory controller.

Abstract: A method and circuit for accurately detecting an output short circuit in a switching regulator. A first transistor and a second transistor are connected in series and driven in a complementary manner. A comparator compares output current, which is generated when the first and second transistors are driven, with a short circuit detection threshold to generate a first short circuit detection signal. A timing controller retrieves the first short circuit detection signal generated by the comparator at a predetermined time to generate a second short circuit detection signal.

Abstract: Receiver circuitry for processing a received Very Low Intermediate Frequency signal wherein the receiver circuitry comprises a main processing path. The main processing path comprises mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal. The receiver circuitry further comprises a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal. The receiver circuitry still further comprises signal summing circuitry arranged to add the DC cancellation signal in anti-phase with the main path signal.

Abstract: A touch panel detection circuit includes current limiting circuitry that has a first portion coupled between a first supply voltage terminal and a first input node and a second portion coupled between a second input node and a second supply voltage terminal. Programmable precharge circuitry connects the first input node to the first supply voltage terminal via a conductive path that is in parallel with the first portion of the current limiting circuitry and precharges the first input node to a predetermined voltage. Comparison circuitry is coupled to the programmable precharge circuitry and to the first input node. The comparison circuitry detects a change in resistance between the first input node and the second input node and provides a signal in response thereto when the comparison circuitry is enabled by the programmable precharge circuitry.

Abstract: A method uses an integrated circuit having a debug status register. The integrated circuit is for being debugged by a hardware debugger external to the integrated circuit and has a processing unit for executing debug software. The debug status register is coupled to the processing unit and is for being coupled to the hardware debugger. The method includes updating the debug status register with hardware status flags arising from running the hardware debugger and software status flags arising from running the debug software. The method further includes masking locations in the debug status register where the hardware status flags are located from being read by the debug software while allowing the hardware status flags and the software status flags to be read by the hardware debugger. This is particularly useful in using the hardware debugger in debugging the debug software.

Abstract: A semiconductor substrate includes a substrate layer and a circuit film formed over the substrate layer. One or more openings are formed in the circuit film and the substrate layer. Conductive plates are formed over the circuit film at the peripheries of the openings. A semiconductor die is attached to the circuit film, below the openings with an adhesive material. A conductive material is disposed in the openings to electrically connect the semiconductor die to the conductive plates.

Abstract: One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

Abstract: A shielding structure is provided for shielding a signal path extending between a first layer and a second layer in an electronic device at a transition region with a transition that extends in a first direction and a second direction orthogonal to the first direction. The shielding structure includes a shielding structure portion, which includes a first shielding via in proximity to a first area of the signal path at the transition; a second shielding via in proximity to a second area of the signal path at the transition; and an area metallization electrically coupled to the first shielding via.

Abstract: A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

Abstract: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance versus voltage characteristic of the cell has a maximum at a non-zero bias voltage.

Abstract: A method and apparatus are provided for mixing a plurality of signals within a predetermined dynamic range without clipping. In the method and apparatus, first and second signal samples are added together to obtain a first intermediate result. Then the first signal sample is multiplied with the second signal sample to obtain a second intermediate result. In one embodiment, the second intermediate result is subtracted from the first intermediate result to obtain a third intermediate result, and the third intermediate result is discarded if the third intermediate result is less than zero. In another embodiment, the second intermediate result is added to the first intermediate result to obtain the third intermediate result, and the third intermediate result is discarded if the third intermediate result is greater than zero. An output signal sample is provided based on the third intermediate result.