Abstract: A multi-mode transmitter (301) is adapted to modulate a data packet (200) communicated by a wireless communications signal. The data packet includes a packet header comprising a preamble (201) and a start of frame delimiter (202), and a data payload comprising a payload data length portion (203) and a payload portion (204). The packet header is modulated with a spread spectrum technique. When transmitting a data payload in one mode, the data payload is also modulated with the spread spectrum technique. When transmitting a data payload in another mode, the data payload is modulated with a non-spread spectrum technique.

Abstract: A stacked semiconductor device assembly (20) includes a device (24) having conductive traces (34) formed therein, and conductive interconnects (28) electrically connected to the conductive traces (34). Another device (26) has conductive traces (44) formed therein and device pads (54) formed on an outer surface (52) of the device (26). A method (120) entails attaching (84) a magnetic core (30) to an outer surface (42) of the device (24) and forming (92) the conductive interconnects (28) on the outer surface (42) using a stud bumping technique such that the interconnects (28) surround the magnetic core (30). The conductive interconnects (28) are coupled (126) with the device pads (54) using thermocompression bonding to couple the device (26) with the device (24) to form a continuous device coil (22) wrapped around the magnetic core (30) from an alternating electrical connection of the traces (34), the conductive interconnects (28), and the traces (44).

Abstract: A method includes providing an integrated circuit having a plurality of debug resources. The debug resources are usable exclusively for debug operations. The debug operations include operations directed by debug software executed by the integrated circuit and operations directed by external debug hardware which is external to the integrated circuit. The method further includes enabling availability of a first portion of the debug resources for use by the debug software, where a second portion of the debug resources are committed for exclusive use by the external debug hardware. The first portion is exclusive of the second portion. The method includes performing operations directed by the debug software using at least one debug resource of the first portion of the debug resources and operations directed by the external debug hardware using at least one debug resource of the second portion of the debug resources.

Abstract: A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

Abstract: A multimodal integrated circuit (IC) is provided, comprising, first (74) and second (76) semiconductor (SC) devices, and first (78) and second (80) integrated passive devices (IPDs) coupled, respectively, to the first (74) and second (76) SC devices, wherein the first IPD (78) overlies the second SC device (76) and the second IPD (80) overlies the first SC device (74) chosen such that the underlying SC device (74, 76) is not active at the same time as its overlying IPD (80, 78). By placing the IPDs (78, 80) over the SC devices (76, 74) a compact IC layout is obtained. Since the overlying IPD (78, 80) and underlying SC (76, 74) are not active at the same time, undesirable cross-talk (68, 69) between the IPDs (78, 80) and the SC devices (76, 74) is avoided. This arrangement applies to any IC having multiple signal paths (RF1, RF2) where the IPDs (78, 80) of a first path (RF1, RF2) may be placed over the SC devices (76, 74) of a second path (RF2, RF1) not active at the same time.

Abstract: A system and method saves power in a system memory of a processing system. A peripheral, a processor, an arbiter and a system memory are coupled to a system communication bus for communicating via the system communication bus. In one form a voltage controller is coupled to the system memory for varying the operating voltage of the system memory based upon whether the data processor or the peripheral is accessing the system memory. In another form a storage buffer is coupled to the memory for receiving and storing data from the memory. The buffer provides at least one signal that is used for either determining a rate at which the storage buffer is being emptied of data or a measure of fullness of the storage buffer. In one form the voltage controller varies the operating voltage of the memory based upon either the rate at which the storage buffer is being emptied of data or the measure of fullness.

Abstract: A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.

Abstract: Timing circuitry may use control circuitry to control calibration circuitry to calibrate a counter so that an adder and a calibration period counter are not required. Concatenation circuitry may be used to concatenate a portion of the counter value and the calibration value to provide a calibrated value to the counter. The results from match circuitry may be used to provide status and control information to a calibration history bit and to an enable circuit. The counter may be an up counter or a down counter.

Abstract: A radio frequency (RF) circuit (100) as disclosed herein is fabricated on a substrate (204, 304) using integrated passive device (IPD) process technology. The RF circuit (100) includes an RF inductor (200, 300) and an integrated inductive RF coupler (202, 302) located proximate to the RF inductor (200, 300). The inductive RF coupler (202, 302), its output and grounding contact pads, and its transmission lines are fabricated on the same substrate (204, 304) using the same IPD process technology. The inductive RF coupler (202, 302) includes a coupling section (212, 306) that is either located inside or outside a spiral of the RF inductor (200, 300). The inductive RF coupler (202, 302) and the RF inductor (200, 300) are cooperatively configured to function as the windings of an RF transformer, thus achieving the desired coupling. The inductive RF coupler (202, 302) provides efficient and reproducible RF coupling without increasing the die footprint of the RF circuit (100).

Abstract: A method includes generating an instruction address value in response to an instruction source event. The method further includes selectively generating a breakpoint request based on the instruction source event and responsive to a comparison of the instruction address value to a breakpoint address value. In one embodiment, selectively generating a breakpoint request includes comparing the instruction source event to an instruction source event type, comparing the instruction address value to a breakpoint address value, and generating the breakpoint request responsive to a match between the first instruction source event type and the instruction source event and a match between the instruction address value and the breakpoint address value.

Abstract: A method includes receiving, at an interconnect, a first transaction request from a first requesting module. The first transaction request includes a request to utilize at least one system resource accessible via the interconnect. The method further includes determining potential interferences at the interconnect expected to occur as a result of a utilization of the at least one system resource by the first requesting module and initiating processing of the first transaction request at the interconnect. The method additionally includes authorizing processing of a second transaction request from a second requesting module during the processing of the first transaction request based on the determined potential interferences.

Abstract: A circuit comprises first and second inverters, first, second, third, and fourth transistors, and an enabling circuit. The first and second inverters each have an input terminal for receiving one of the first or second input signals, an output terminal, and first and second supply terminals. The first transistor is coupled to a first power supply terminal, to the output terminal of the second inverter, and to the first inverter. The second transistor is coupled to the first power supply terminal, to the output terminal of the first inverter, and to the first supply terminal of the second inverter. The third and fourth transistor are coupled to the second supply terminals of the first and second inverters, respectively, and each includes a control electrode and a second current electrode. The enabling circuit is for controlling the third and fourth transistors to reduce a leakage current in the circuit.

Abstract: A virtual address cache and a method for sharing data. The virtual address cache includes: a memory, adapted to store virtual addresses, task identifiers and data associated with the virtual addresses and the task identifiers; and a comparator, connected to the memory, adapted to determine that data associated with a received virtual address and a received task identifier is stored in the memory if at least a portion of the received virtual address equals at least a corresponding portion of a certain stored virtual address and a stored task identifier associated with the certain stored virtual address indicates that the data is shared between multiple tasks.

Abstract: An address decoder that sets an address of a module connected to a bus includes a level comparator, an edge detector, and an output decoder. The level comparator compares an SDA signal, which is input to an SDA terminal, with an address selection signal, which is input to an ADDR terminal, and outputs a comparison result. When the two signals match, the comparison is repeated until slave addresses are all received. When the two signals do not match, subsequent comparisons are not performed. The edge detector detects an edge of the address selection signal input to the ADDR terminal. The output decoder sets an address corresponding to the connected destination of the ADDR terminal to determine an address of a slave module connected to the address decoder.

Abstract: A first value from a set of bit cells of a sector of a non-volatile memory device is sensed based on a first read reference. A second value from the set of bit cells is sensed based on a second read reference different than the first read reference. A third read reference for a first subsequent access to the sector of the non-volatile memory device is determined based on at least one of the first read reference and the second read reference in response to determining a first error code condition associated with the first value and a second error code condition associated with the second value represent different error code conditions.

Abstract: A memory includes a selection circuit and a write assist circuit. The selection circuit has a first input, a second input coupled to a first power supply voltage terminal, an output coupled to a power supply terminal of each of a plurality of memory cells, and a control input for receiving a write assist control signal. The write assist circuit is coupled to the first input of the selection circuit for reducing a voltage at the power supply terminal of each of the plurality of memory cells during a write operation and in response to an asserted write assist enable signal. The write assist circuit comprises a P-channel transistor and a bias voltage generator. The P-channel transistor is for reducing the voltage at the power supply terminal of each of the plurality of memory cells during the write operation. The bias voltage generator is for providing a variable bias voltage to the P-channel transistor.

Abstract: A reference voltage regulation circuit (143) is provided in which one or more input voltage signals (Vref, Vref?) are selectively coupled to a configurable amplifier (114) which is coupled through a sample and hold circuit (120) to a voltage follower circuit (122) which is coupled in feedback to the configurable amplifier (114) for generating an adjusted output voltage at a circuit output (130), where the voltage follow circuit comprises a resistor divider circuit (126) that is controlled by a calibration signal (Cal<n:0>) generated by a counter circuit (128) selectively coupled to the output of the configurable amplifier when configured as a comparator for generating the calibration signal in response to a clock signal, where the calibration signal represents a voltage error component (Verror, Voffset) that is removed from the circuit output when the calibration signal is applied to the resistor divider circuit during normal operational.

Abstract: A power detector comprises a pair of transistor amplifier elements having respective control terminals for receiving with opposite polarities a radio/mm-wave frequency signal whose power is to be detected. Respective alternately-conductive parallel amplifier paths are controlled by the control terminals. A low pass filter and current mirror is responsive to the combined currents flowing in the parallel amplifier paths for producing a low pass filtered signal. A detector output stage is responsive to the low pass filtered signal. Each of the pair of amplifier elements includes a respective impedance through which flows current from the respective amplifier path and current from the respective control terminal.

Abstract: A buffer for managing the order of data packages arriving at the buffer, wherein the buffer includes a first window, having a predetermined size defined by a first and a second extreme, and the first window is included within a second window. The buffer includes a filter for determining the time stamp of an arriving data package to determine if the arriving data package has an expected location included inside or outside the first window based on the time stamp. The buffer also includes a buffer module for locating the arriving data package in the expected location or for moving the first window by a predetermined distance to a position, without changing the size of the first window, to accommodate the expected location.

Abstract: Method and apparatus for designing an integrated circuit by calculating an optimised reticle layout design from an IC layout design and a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the IC layout design comprises features defined by a plurality of boundaries. Approximating the plurality of boundaries to generate an approximated IC layout design suitable for the manufacture of the IC. Performing OPC simulation on at least a portion of the approximated IC layout design.