Abstract: Test circuitry for determining whether a memory can operate at a lower operating voltage. The test circuitry includes a sense circuit having a delayed sensing characteristic as compared to other sense amplifier circuits of the memory. With this circuitry, the test circuitry can determine if the sense circuit can provide valid data under more severe sensing conditions. In one example, the sense circuit includes a delay circuit in the sense enable signal path. If sense circuit can provide data at more server operating conditions, then the memory operating voltage can be lowered.

Abstract: Embodiments of a cascode amplifier (CA) include a bottom transistor with a relatively thin gate dielectric and higher ratio of channel length to width and a series coupled top transistor with a relatively thick gate dielectric and a lower ratio of channel length to width. A cascode current mirror (CCM) is formed using a coupled pair of CAs, one forming the reference current (RC) side and the other forming the mirror current side of the CCM. The gates of the bottom transistors are tied together and to the common node between the series coupled bottom and top transistors of the RC side, and the gates of the top transistors are coupled together and to the top drain node of the RC side. The area of the CCM can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.

Abstract: A dual current path LDMOSFET transistor (40) is provided which includes a substrate (400), a graded buried layer (401), an epitaxial drift region (404) in which a drain region (416) is formed, a first well region (406) in which a source region (412) is formed, a gate electrode (420) formed adjacent to the source region (412) to define a first channel region (107), and a current routing structure that includes a buried RESURF layer (408) in ohmic contact with a second well region (414) formed in a predetermined upper region of the epitaxial layer (404) so as to be completely covered by the gate electrode (420), the current routing structure being spaced apart from the first well region (406) and from the drain region (416) on at least a side of the drain region to delineate separate current paths from the source region and through the epitaxial layer.

Abstract: Apparatus and methods are provided for converting an analog input signal to a digital output value. A quantization circuit comprises an input node and a comparator array, wherein each comparator of the comparator array is coupled to the input node. A voltage divider arrangement is coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array. The comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator. A control node is coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node.

Abstract: Apparatus are provided for continuous-time sigma-delta modulators. The sigma-delta modulator comprises an input node for an input signal and a quantizer configured to convert an analog signal to a digital value. A main feedback arrangement is coupled to the quantizer and configured to delay the digital value by a first delay period and generate a main feedback signal by digitally filtering the first delayed value. A compensation feedback arrangement is coupled to the quantizer and configured to delay the digital value by a second delay period, wherein the second delay period is not influenced by the first delay period, and generate a compensation feedback signal by digitally filtering the second delayed value. A forward signal arrangement produces the analog signal based on the input signal, the main feedback signal, and the compensation feedback signal.

Abstract: There is a method for forming a semiconductor device. Portions of a sacrificial layer are removed to expose a first seed layer region. The first seed layer region corresponds to a first semiconductor region, and a remaining portion of the sacrificial layer corresponds to a second semiconductor region. An epitaxial semiconductor material is deposited over the first seed layer region. A capping layer is formed to overlie the epitaxial semiconductor material and the remaining portion of the sacrificial layer. Portions of the capping layer are removed to form a capping structure that overlies a part of the remaining portion of the sacrificial layer. Portions of the sacrificial layer not covered by the capping structure are removed to form a sacrificial structure having sidewalls. Fin structures are formed adjoining the sidewalls by depositing a semiconductor material along the sidewalls. Portions of the capping structure are removed to expose portions of sacrificial layer between adjacent fin structures.

Abstract: A processing device includes a timer and a processor core configured to execute an instruction during a debug session. The processing device further includes a timer control module configured to selectively enable/disable the timer based on a characteristic of the instruction. Another processing device includes a timer, a processor core configured to single step execute a sequence of instructions during a debug session, and a timer control module configured to selectively enable/disable the timer during single step execution of each instruction of the sequence of instructions.

Abstract: A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises providing a semiconductor substrate, providing a first layer of a first semiconductor material over the semiconductor substrate and providing a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material. The method further comprises removing a portion of the first layer and a portion of the second layer selectively according to the different rates of removal so as to provide a lateral layer and the vertical channel portion of the inverted T shaped channel structure and removing a portion of the lateral layer so as to provide the horizontal channel portion of the inverted T shaped channel structure.

Abstract: A switch controller has a charge pump, a selector switch connected to the charge pump, and a pre-charge power supply input connectable to the input of the selector switch. For each of the output channels being controlled, a power control switch is connected to an output of the selector switch. In response to commands, output channels are enabled and disabled, causing corresponding actions in the power control switches. When an output channel is to be activated, the output channel is selected by the selector switch and the pre-charge power supply connected to the input of the selector switch. The charging is completed by the charge pump and the enabled status of the power control switch is maintained by the charge pump.

Abstract: A method of managing a memory of an apparatus the apparatus executing one or more processes using the memory. The method comprises maintaining a plurality of lists of identifiers, wherein each list has an associated size value and an associated threshold corresponding to a maximum number of identifiers in that list, wherein each identifier identifies a corresponding region of the memory that had been allocated for a process but that is currently not required by any of the one or more processes, and wherein the size of a region of the memory identified by an identifier of a list equals the size value associated with that list.

Abstract: A data processing system includes one or more processing unit arranged to execute sets of instructions stored in the data processing system. The sets may include two or more application sets, each forming an application sets and including instructions for scheduling for the application an event at a future point in time. The event may require the processing unit to be in an active mode. The sets may further include rescheduling instructions for receiving from the applications information about the scheduled events and determining whether or not one or more of the events can be rescheduled and rescheduling a reschedulable event to a new point in time. The sets may further include mode control instructions for controlling the processing unit to be in the active mode during a time interval which includes the new point in time and to be in a low power mode in which the processing unit consumes less energy than in the active mode during a period of time adjacent to the time interval.

Abstract: A band-gap voltage reference circuit comprising first and second branches respectively including first and second groups of transistors of different emitter current conduction areas and current sources for running the first and second groups of transistors at different emitter current densities to generate respective base-emitter voltages, and output terminals connected to receive a regulated voltage (Vout) which is a function of the base-emitter voltages of the first and second groups of transistors. Each of the first and second groups includes at least one npn-type transistor and at least one pnp transistor connected with their emitter-collector paths in series in the respective one of the branches so as to present cumulated base-emitter voltages across the respective group.

Abstract: A wireless communication unit has two or more communication modes including one or more mobile phone mode, in which mobile phone mode the wireless communication unit is able to transmit or receive wireless signals via an antenna from and/or to a mobile phone network in accordance with a communication protocol. The unit includes a baseband module and a radiofrequency module. A radiofrequency interface of the baseband module is connected to the radiofrequency module, for receiving and/or transmitting baseband signals from and/or to the radiofrequency module. The radiofrequency module includes a baseband interface, for receiving and/or transmitting the baseband signals to the baseband module and an antenna interface (AI) connectable to an antenna for receiving and/or transmitting radiofrequency signals from and/or to the antenna. A clock system is connected to the radiofrequency interface and the baseband interface.

Abstract: A secure computing device (14) includes a secure processing section (30) having a tamper detection circuit (58) and a monotonic counter (68). The tamper detection circuit (58) detects an event which suggests that the trust associated with the secure processing section (30) may have been compromised. When such an event is detected, a security breach is declared and trusted software (38) is disabled. After a security breach is declared, the monotonic counter (68) may be reclaimed. The monotonic counter (68) provides a monotonic count value (70) that includes an LSB portion (80) and an MSB portion (82). The LSB portion (80) is obtained from a binary counter (72). The MSB portion (82) is obtained from a register (84) of independent one-time-programmable bits. The monotonic counter (68) is reclaimed by programming one of the one-time programmable bits to guarantee that future counting of the monotonic counter will be monotonic relative to all past counting.

Abstract: A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal of the phase locked loop. The phase detector provides a pulse having a width indicative of the phase difference. A phase measurement module determines a digital value based on the pulse width. Accordingly, the digital value provides an indication of the phase difference between the reference clock signal and the output clock signal. A series of the digital values can be recorded to indicate how the phase difference varies over time, thereby providing a useful characterization of device behavior.

Abstract: A circuit includes a voltage regulator (208) for outputting a voltage at a regulated level, a protection circuit (260), and a load circuit (210) coupled to the voltage regulator. The protection circuit includes means for preventing the voltage regulator from outputting a voltage at a level higher than the regulated level during a start-up period of the voltage regulator.

Abstract: A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser. In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time.

Abstract: Digital complex tone generators include a first tone generator configured to generate a first digital tone with selectable first characteristics including a first frequency, a first phase, and a first amplitude; a second tone generator configured to generate a second digital tone with selectable second characteristics including a second frequency, a second phase, and a second amplitude; and a generator adder configured for combining the first tone and the second tone to provide a digital complex tone with programmable characteristics. Corresponding methods include initializing a first and second tone generators based on, respective, selected frequencies, phases, and amplitudes; iteratively generating a first digital tone and a second digital tone; and combining these two tones to provide the digital complex tone.

Abstract: A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.

Abstract: A disclosed semiconductor fabrication process includes forming a first bonding structure on a first surface of a cap wafer, forming a second bonding structure on a first surface of a device wafer, and forming a device structure on the device wafer. One or more eutectic flow containment structures are formed on the cap wafer, the device wafer, or both. The flow containment structures may include flow containment micro-cavities (FCMCs) and flow containment micro-levee (FCMLs). The FCMLs may be elongated ridges overlying the first surface of the device wafer and extending substantially parallel to the bonding structure. The FCMLs may include interior FCMLs lying within a perimeter of the bonding structure, exterior FCMLs lying outside of the bonding structure perimeter, or both. When the two wafers are bonded, the FCMLs and FCMCs confine flow of the eutectic material to the region of the bonding structure.