Abstract: A voltage detector device is disclosed that includes a coarse-range voltage detector and a fine-range voltage detector. The fine-range voltage detector is configured to remain inactive, so that it consumes a relatively small amount of power, while a monitored voltage is outside a first specified range. In response to determining that the monitored voltage is within the first specified range, the coarse-range voltage detector activates the fine-range voltage detector so that it can monitor the voltage. In response to the fine-voltage monitor determining the voltage falls within a second specified range, the fine-range voltage detector provides a signal to a functional module of an electronic device so that the functional module can provide a defined response, such as executing an interrupt routine.

Abstract: An integrated circuit, including: (i) a power gated circuit which power supply is shut down during a low-power period; (ii) a retention circuit, coupled to the power gated circuit during at least a portion of a non-low-power period, the retention circuit is adapted to store, during the low-power period, state information reflecting a state of the power gated circuit before the low-power period started; (iii) a first portion of the power grid, coupled to the retention circuit and to a first end of a power supply switch, adapted to provide to the retention circuit a supply voltage during the low-power period and during a non-low-power period; wherein the power supply switch is open during the low-power period and is closed during the non-low-power period; and (iv) a second portion of the power grid, coupled to a second end of the power supply switch and to the power gated circuit; adapted to supply a gated supply voltage to the power gated circuit during the non-low-power period.

Abstract: An electronic device can include a substrate including a trench having a bottom and a first wall. The electronic device can also include a first gate electrode within the trench and adjacent to the first wall and overlying the bottom of the trench, a second gate electrode overlying the substrate outside of the trench, and a third gate electrode within the trench and adjacent to the first gate electrode and overlying the bottom of the trench. The electronic device can also include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies adjacent to the first wall of the trench. Processes of forming and using the electronic device are also described.

Abstract: A packaged semiconductor device includes an interconnect layer over a first side of a polymer layer, a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer, a first conductive element over a second side of the polymer layer, wherein the second side is opposite the first side, and a connector block within the polymer layer. The connector block has at least one electrical path extending from a first surface of the connector block to a second surface of the connector block. The at least one electrical path electrically couples the interconnect layer to the first conductive element. A method of forming the packaged semiconductor device is also described.

Abstract: A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.

Abstract: In the field of immersion lithography, it is known to provide a liquid between an optical exposure system and a wafer carrying layers of photosensitive material to be irradiated with a pattern by the optical exposure system. However, bubbles are known to form or exist in the liquid, sometimes close to a surface of the wafer resulting in scattering of light emitted from the optical exposure system. The scattering causes the pattern recorded in the layers of photosensitive material to be corrupted, resulting in defective wafers. Therefore, the present invention provides a bubble displacement apparatus comprising a drive signal generator for driving a force generator arranged to generate a force in response to a drive signal generated by the drive signal generator. The force generated urges the bubble away from the surface.

Abstract: A wireless communication device comprises a frequency generation circuit employing a crystal oscillator operably coupled to a fractional-based synthesiser and a voltage-controlled oscillator. The fractional-based synthesiser utilises a ratio between an integer value and a fractional value to set a radio frequency signal of the voltage-controlled oscillator. An automatic frequency control scaling sub-system is operably coupled to a fractional-based synthesiser and configured to receive and use an AFC word to frequency scale the fractional value in a multiplicative manner to set a radio frequency supported by the fractional-based synthesiser. Preferably, an automatic frequency generation sub-system utilises Absolute Radio Frequency Channel Number and the cyclical nature of the fractional value. In this manner, a saving on hardware and software overheads associated with frequency channel selection for fractional-N type synthesizers can be made.

Abstract: A wireless mobile device comprising a tuner for converting a received radio frequency signal to a base band signal or intermediate frequency signal and providing the base band signal or intermediate frequency signal to a receiver, wherein the receiver is arranged to provide received data associated with the base band signal or intermediate frequency signal to an application processor for storage in memory, wherein the application processor is arranged to extract the data from memory in an interleaved form and perform error correction on the interleaved data.

Abstract: An amplifier has an input stage coupled to a current mirror for providing a first control signal. A gain boosting stage has first and second sections, each having first and second inputs and an output. The first input of the first section is coupled to the input stage. The second input of the first section is a first node between a source and a drain of a first pair of series-coupled transistors. The first input of the second section is coupled to the current mirror. The second input of the second section is a second node between a source and a drain of a second pair of series-coupled transistors. A pre-driver stage has inputs coupled to the input stage and the gain boosting stage. The pre-driver stage provides inputs to the gain boosting stage and receives outputs from the gain boosting stage prior to coupling to an output stage.

Abstract: Techniques and technologies are provided for compressing differential samples of bandwidth-limited data and coding the compressed differential samples to reduce bandwidth and power consumption when communicating bandwidth-limited data over a serial interface which couples one integrated circuit to another integrated circuit.

Abstract: A technique for implementing compensatory feedback in a continuous-time sigma-delta modulator includes providing, based on an analog input signal, a digital output signal at an output of a quantizer circuit of the continuous-time sigma-delta modulator. A functionality of the quantizer circuit is then controlled based on the digital output signal.

Abstract: A circuit and a method for reducing output noise when a pulse width modulation mode is started. A pulse width modulation circuit generates a first pulse signal having a duty cycle that is in accordance with an output voltage of a regulator circuit. A drive circuit generates the output voltage from an input voltage in response to the first pulse signal provided from the pulse width modulation circuit. A feed forward circuit controls the pulse width modulation circuit in a manner to generate the first pulse signal having a duty cycle that maintains the output voltage at a desired level before the pulse width modulation circuit provides the first pulse signal to the drive circuit.

Abstract: A packaged electronic device (20) includes a die pad (30), leads (32) arranged around the die pad (30), and a die (24) attached to an upper surface (34) of the die pad (30) and electrically connected to the leads (32). A packaging material (28) encapsulates the die pad (30), the die (24), and the leads (32). The die pad (30) includes indentations (42) formed in the upper surface (34) along a sidewall (38) of the die pad (30). The die pad (30) further includes indentations (44) formed in a lower surface (36) of the die pad (30) along the sidewall. The packaging material (28) fills the indentations (42, 44) thereby promoting adhesion between the die pad (30) and the packaging material (28) so that the die pad (30) and packaging material (28) cannot readily delaminate.

Abstract: A method for configuring IO pads, the method includes determining a current configuration of multiple IO pads of an integrated circuit and whereas the method is characterized by generating multiple boundary scan register words that comprise Configuration information; and repeating the stage of serially writing a certain boundary scan register word to a boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits. A device that includes a core, connected to a boundary scan register, a TAP controller and multiple IO pad circuits, the device is characterized by including a control circuit adapted to determine a current configuration of the IO pads, to generate multiple boundary scan register words that comprise configuration information; and to control a repetition of: writing a certain boundary scan register word to the boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits.

Abstract: Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus (200) includes a metal-oxide-semiconductor field-effect transistor (MOSFET) (210). MOSFET (210) includes a doped substrate (2210) with a source formed proximate a substrate tie (2224) and a substrate tie (2250) adjacent substrate (2210). A ground rail (255) is coupled to the source and substrate tie (2224), and a ground rail (285) is coupled to substrate tie (2250). Ground rails (255) and (285) are configured to be coupled to different ground networks (250 and 280). One method includes producing a model of a semiconductor device including a standard semiconductor cell (710). The semiconductor cell is identified as a noise-sensitive or a noise-producing semiconductor cell (720), and the semiconductor cell is replaced with a corresponding noise-aware semiconductor cell (730).

Abstract: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) includes a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) includes one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) is defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).

Abstract: The invention relates to an adaptive Radio Frequency (RF) filter (11), which is particularly useful as an RF filter in Wireless Local Area Networks (WLAN's). As greater demands are placed on RF systems, for example in WLAN's in order to increase channel capacity by utilizing available bandwidth, corresponding demands are placed upon performance and tolerance of components used in FR circuits.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent to the gate structure. The method further includes forming a recess in the semiconductor layer, the recess aligned to the high-k sidewall spacer. The method further includes forming an in-situ doped epitaxial material in the recess, the epitaxial material having a natural lattice constant different from a lattice constant of the semiconductor layer to create stress in a channel region of the semiconductor device.

Abstract: A method provides a data acquisition message of a data processing system to an external port thereof. Configuration information is written to a configuration register. It is determined if the configuration information identifies a data acquisition operation. If the data acquisition operation has been identified, data corresponding to the configuration information is written to a data register. The data in the data register and the configuration information in the configuration register are formatted into the data acquisition message. The data acquisition message is sent to the external port of the data processing system.

Abstract: An inverter circuit has a digital signal amplitude converter having an input coupled to an inverter circuit input node, and an amplitude converter output. A positive threshold voltage compensation generator has a positive threshold voltage compensation generator input coupled to the amplitude converter output. A negative threshold voltage compensation generator has a negative threshold voltage compensation generator input coupled to the inverter circuit input node, and a negative threshold voltage compensation generator output. A multiplexer has a first input coupled to the positive threshold voltage compensation generator output, a second input, coupled to the negative threshold voltage compensation generator output, and a multiplexer output. An inverter module has an output providing an inverter circuit output node, and an inverter module input is coupled to the multiplexer output.