Patents Assigned to Freescale
  • Short circuit and over-voltage protection for a data bus
    Patent number: 7835124
    Abstract: An apparatus for protecting a device against an over-voltage condition that is in excess of its breakdown voltage includes a detector for detecting the over-voltage condition and a protection circuit for protecting the device in response to detection of the over-voltage condition. The protection circuit may include a transmission gate and a PMOS transistor for producing a protection signal. The protection signal may be applied to a gate and/or a drain and/or a source and/or a well of the device such that a voltage across the device does not exceed the breakdown voltage. The protection signal may be derived from the over-voltage condition independent of whether a supply of power to the device is present.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: November 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gopal Krishna Siddhartha, Kulbhushan Misri, Venkataramana Pandiri
  • Semiconductor die with die pad pattern
    Patent number: 7834466
    Abstract: A structure includes a semiconductor die that has an arrangement of die pads on a surface of the semiconductor die. A first row of die pads consists of a first group of four die pads and run in a first direction. A second row of die pads are adjacent to the first row and consist of a second group of four die pads running in the first direction. The second row begins at a first offset in the first direction from where the first row begins. A third row of die pads are adjacent to the second row and comprise a third group of four die pads that run in the first direction. The third row begins at a second offset in the first direction from where the second row begins. This allows for relatively easy access to all of the die pads.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: November 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert J. Wenzel, Trung Q Duong, Ilan Lidsky
  • ADDRESS TRANSLATION TRACE MESSAGE GENERATION FOR DEBUG
    Publication number: 20100287417
    Abstract: A data processing system and method generates debug messages by permitting an external debug tool to have real-time trace functionality. A data processor executes a plurality of data processing instructions and uses a memory for information storage. Debug module generates debug messages including address translation trace messages. A memory management unit has address translation logic for implementing address translation to translate addresses between virtual and physical forms. The debug module includes message generation module that is coupled to the memory management unit for receiving notice when one or more address translation mappings are modified. The message generation module generates an address translation trace message in response to a detection of a modification of an address translation mapping occurs and provides the address translation trace message external to the debug module.
    Type: Application
    Filed: May 5, 2009
    Publication date: November 11, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Richard G. Collins
  • REGULATED VOLTAGE SYSTEM AND METHOD OF PROTECTION THEREFOR
    Publication number: 20100283444
    Abstract: A system comprises a voltage regulator operably coupled to an external component, a voltage regulator reset circuit and at least one functional element supplied with a voltage by the voltage regulator. The voltage regulator reset circuit is arranged to repetitively reset the voltage regulator upon disconnection of the external component.
    Type: Application
    Filed: January 18, 2006
    Publication date: November 11, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Arlette Marty-Blavier, Philippe Lance, Stephan Ollitrault, Yean Ling Teo
  • Microelectromechanical systems component and method of making same
    Patent number: 7829366
    Abstract: A microelectromechanical systems (MEMS) component 20 includes a portion 32 of a MEMS structure 30 formed on a semiconductor substrate 34 and a portion 36 of the structure 30 formed in a non-semiconductor substrate 22. The non-semiconductor substrate 22 is in fixed communication with the semiconductor substrate 34 with the portion 32 of the MEMS structure 30 being interposed between the substrates 34 and 22. A fabrication method 96 entails utilizing semiconductor thin-film processing techniques to form the portion 32 on the semiconductor substrate 34, and utilizing a lower cost processing technique to fabricate the portion 36 in the non-semiconductor substrate 22. The portions 32 and 36 are coupled to yield the MEMS structure 30, and the MEMS structure 30 can be attached to another substrate as needed for additional functionality.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: November 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Melvy F. Miller, Daniel N. Koury, Jr., Lianjun Liu
  • Micromechanical device with piezoelectric and electrostatic actuation and method therefor
    Patent number: 7830066
    Abstract: A MEMS device uses both piezoelectric actuation and electrostatic actuation and also provides enough electrostatic force to enable very low voltage operation. As the electrostatic actuation uses DC and the piezoelectric actuation uses high frequency, the structure of the device minimizes the coupling of the two actuator structures to reduce noise. In addition, for some embodiments, the location of the physical structures of the piezoelectric actuator and electrostatic actuator generates higher contact force with lower voltage. For some embodiments, the piezoelectric actuator and electrostatic actuator of the device are connected at the contact shorting bar or capacitor plate location. This makes the contact shorting bar or capacitor plate the focal point of the forces generated by all of the actuators, thereby increasing the switch contact force.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: November 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Lianjun Liu
  • Level realignment following an epitaxy step
    Patent number: 7830027
    Abstract: The invention relates to inter-level realignment after a stage of epitaxy on a face (31) of a substrate (30), comprising the production of at least one initial guide mark (32) on the face of the substrate, this initial guide mark being designed so as to be transferred, during epitaxy, onto the surface of the epitaxied layer (36). The initial guide mark (32) is produced in such a way that, during epitaxy, its edges create growth defects that propagate as far as the surface of the epitaxied layer (36) to provide a transferred guide mark (37) on the surface of the epitaxied layer (36) reproducing the shape of the initial guide mark (32) and in alignment with the initial guide mark.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: November 9, 2010
    Assignees: Commissariat a l'Energie Atomique, Freescale Semiconductor, Inc.
    Inventors: Bernard Diem, Eugene Blanchet, Bishnu Gogoi
  • Interconnect for chip level power distribution
    Patent number: 7829997
    Abstract: A semiconductor device (601) is provided which comprises a substrate (603); a semiconductor device (605) disposed on said substrate and having a first major surface; a first metal strap (615) which is in electrical contact with said substrate and which is adapted to provide power to a first region (608) of said semiconductor device; and a second metal strap (616) which is in electrical contact with said substrate and which is adapted to provide ground to a second region (609) of said semiconductor device.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: November 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kevin J. Hess, Chu-Chung Lee, James W. Miller
  • Selective timer control during single-step instruction execution
    Patent number: 7831862
    Abstract: A processing device includes a timer and a processor core configured to execute an instruction during a debug session. The processing device further includes a timer control module configured to selectively enable/disable the timer based on a characteristic of the instruction. Another processing device includes a timer, a processor core configured to single step execute a sequence of instructions during a debug session, and a timer control module configured to selectively enable/disable the timer during single step execution of each instruction of the sequence of instructions.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: November 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Jason T. Nearing
  • Semiconductor structure pattern formation
    Patent number: 7829447
    Abstract: Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an oxidation process that grows oxide on the sidewalls of the channel pattern structure and the top surface of the source/drain pattern structures. The remaining oxidizable material of the channel pattern structure is subsequently removed leaving a hole between two portions of the oxide layer. These two portions are used in one embodiment as a mask for patterning the semiconductor layer to form two fins. This patterning also leaves the source/drain structures connected to the fins.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: November 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Rode R. Mora, Tab A. Stephens, Tien Ying Luo
  • Method and apparatus for data allocation in an overlap-enabled communication system
    Patent number: 7830855
    Abstract: A communication system is dynamically configured to use some or all of the communication channel bandwidth. Regions of the communication channel are prioritized, and bandwidth is allocated in accordance with priorities and requested data rate.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: November 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Howard E. Levin, Kenneth J. Cavanaugh, Jeffrey P. Gleason, Peter R. Molnar
  • Exception-based timer control
    Patent number: 7831818
    Abstract: A processing device includes a timer and an exception controller configured to provide an exception indicator representative of a first exception. The processing device further includes a timer controller configured to selectively enable/disable the timer in response to the exception and based on a characteristic of the exception. A method of utilizing the processing device includes receiving an exception and determining a characteristic of the exception. The method further includes, at a first time, selectively enabling/disabling the timer of the processing device based on the characteristic, and, at a second time subsequent to the first time, accessing a count value stored at the timer. The method further includes providing the count value for output from the processing device.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: November 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: William C. Moyer
  • SEMICONDUCTOR PROCESSING METHOD
    Publication number: 20100275951
    Abstract: A process for treating the surface of a substrate in the manufacture of a semiconductor device. The process comprises providing a concentrated acid or base, a peroxide and water, and delivering the acid or base, the peroxide and the water to the surface of the substrate. The acid or base and the water are delivered separately to the surface of the substrate and allowed to mix on the surface, and the water is delivered in pulses. The present invention also provides an apparatus adapted to carry out this process.
    Type: Application
    Filed: January 9, 2008
    Publication date: November 4, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Tony Vessa
  • METHODOLOGY FOR PROCESSING A PANEL DURING SEMICONDUCTOR DEVICE FABRICATION
    Publication number: 20100279467
    Abstract: A method (20, 104) for processing a panel (26, 128) during semiconductor device (52) fabrication entails forming grooves (72, 142) in a surface (34, 132) of the panel (26, 128) coincident with a dicing pattern (54) for the panel (26, 128). The grooves (72, 142) extend partially through the panel (26, 128) so that the panel (26, 128) remains intact. The grooves (72, 142) relieve stress in the panel (26, 128) to reduce panel (26, 128) warpage, thus enabling the panel (26, 128) to be reliably held on a support structure (88, 98, 138) via vacuum when undergoing further processing, such as solder printing (86). The method (20, 104) further entails, dicing (96, 152) through the panel (26, 128) from the surface (34, 132) in accordance with the dicing pattern (54) while the panel (26, 128) is mounted on the support structure (98, 138) to singularize the semiconductor devices (52).
    Type: Application
    Filed: April 29, 2009
    Publication date: November 4, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Alan J. Magnus, Justin E. Poarch, Jason R. Wright
  • SEMICONDUCTOR DEVICE AND APPARATUS INCLUDING SEMICONDUCTOR DEVICE
    Publication number: 20100277205
    Abstract: A semiconductor device includes a substrate on which an electronic circuit is provided. One or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an amount of a current flowing between the substrate and at least one of the at least one pad. A control unit is connected to the current meter and the electronic circuit, for controlling the electronic circuit based on the measured parameter.
    Type: Application
    Filed: December 6, 2007
    Publication date: November 4, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Andreas Roth, Hubert Bode, Andreas Laudenbach, Engelbert Wittich, Stephan Lehmann
  • Digital pulse width modulation for half bridge amplifiers
    Patent number: 7825726
    Abstract: A switching amplifier drives a load or audio transducer. A digital integral noise shaping circuit converts a digital input such as audio content to an output digital pulse width modulated signal using an integrator. The integrator integrates the digital input, a variable frequency reference pulse width modulated signal and an inverse of the output digital pulse width modulated signal. A half bridge amplifier receives the output digital pulse width modulated signal and drives the load or audio transducer. A variable frequency generator generates the variable frequency reference pulse width modulated signal with an approximately equal duty ratio or alternatively varies the variable frequency pulse width modulated signal above and below about a fifty percent duty ratio.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: November 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Pallab Midya, Matthew R Miller, William J Roeckner
  • Technique for interconnecting integrated circuits
    Patent number: 7827336
    Abstract: Two integrated circuit die each having a processing core and on-board memory are interconnected and packaged together to form a multi-chip module. The first die is considered primary and the second die is considered secondary are connected through an interposer. The first and second die may be the same design and thus have the same resources such as peripherals and memory and preferably have a common system interconnect protocol. The core of the second die is disabled or at least placed in a reduced power mode. The first die includes minimal circuit for interconnecting to the second die. The second die has some required interface circuitry and an address translator. The result is that the core of the first die can perform transactions with the memory and other resources of the second integrated circuit as if the memory and other resources were on the first die.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: November 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gary L. Miller, Ronald W. Stence
  • LED driver with dynamic power management
    Patent number: 7825610
    Abstract: Power management in a light emitting diode (LED) system having a plurality of LED strings is disclosed. A voltage source provides an output voltage to drive the LED strings. An LED driver monitors the tail voltages of the active LED strings to identify the minimum, or lowest, tail voltage and adjusts the output voltage of the voltage source based on the lowest tail voltage. The LED driver can adjust the output voltage so as to maintain the lowest tail voltage at or near a predetermined threshold voltage so as to ensure that the output voltage is sufficient to properly drive each active LED string with a regulated current in view of pulse width modulation (PWM) performance requirements without excessive power consumption.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: November 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bin Zhao, Jack W. Cornish, Brian B. Horng, Victor K. Lee, Andrew M. Kameya
  • Testing non-volatile memory devices for charge leakage
    Patent number: 7826287
    Abstract: The method of and apparatus for testing a floating gate non-volatile memory semiconductor device comprising an array of cells including floating gates for storing data in the form of electrical charge. The method includes applying a test pattern of said electrical charge to the floating gates, exposing the device to energy to accelerate leakage of the electrical charges out of the cells, and subsequently comparing the remaining electrical charges in the cells to the test pattern. The energy is applied in the form of electromagnetic radiation of a wavelength such as to excite the charges in the floating gates to an energy level sufficient for accelerating charge loss from the floating gates of defective cells relative to charge loss from non-defective cells. The wavelength is preferably in the range of 440 to 560 nm.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: November 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Laurence Morancho-Montagner, Jean-Louis Chaptal, Serge De Bortoli, Gerard Sarrabayrouse
  • Circuit for a low power mode
    Patent number: 7825720
    Abstract: A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: November 2, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, David R. Bearden, Kenneth R. Burch, Charles E. Seaberg