Patents Assigned to Freescale
  • Publication number: 20100333048
    Abstract: Method and apparatus for designing an integrated circuit by calculating an optimised reticle layout design from an IC layout design and a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the IC layout design comprises features defined by a plurality of boundaries. Approximating the plurality of boundaries to generate an approximated IC layout design suitable for the manufacture of the IC. Performing OPC simulation on at least a portion of the approximated IC layout design.
    Type: Application
    Filed: August 16, 2006
    Publication date: December 30, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Kevin Dean Lucas, Robert Elliott Boone, Yves Rody
  • Patent number: 7858487
    Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Edward O. Travis, Mehul D. Shroff, Donald E. Smeltzer, Traci L. Smith
  • Patent number: 7861291
    Abstract: A method, data processing system, and computer program product are provided for retrieving access rules using a plurality of subtables. An incoming packet that includes fields of data is received from a network. A key is formed from the fields, the key includes a number of subkeys. The subkeys are selected and each of the selected subkeys is used to search a different subtable. If a subtable entry is a pointer, a next level subtable is searched until a failure or data is encountered. If a failure occurs, a default rule is applied. If data is encountered, the key is masked using a stored mask value. The resulting masked key is compared to a stored rule. If they match, the identified rule is applied, otherwise the default rule is applied.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: December 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David B. Kramer, Chris P. Thron, Bernard Karl Gunther
  • Patent number: 7858482
    Abstract: A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: December 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Christopher C. Hobbs, Srikanth B. Samavedam
  • Patent number: 7859299
    Abstract: A method and circuit includes providing at least one conductor for receiving an input signal. A termination circuit and a clamp circuit are coupled to the at least one conductor. The termination circuit is enabled while the clamp circuit remains enabled. The clamp circuit is disabled. After disabling the clamp circuit, while the termination circuit remains enabled, both a first differential comparator and a second differential comparator are enabled. The first differential comparator receives a first differential input signal at a first input and a second differential input signal at a second input. The second differential comparator detects when a difference between the first differential input signal and the second differential input signal is greater than a predetermined value and enables transfer of an output of the first differential comparator to a memory controller.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: December 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James G. Gay, Carlos A. Greaves
  • Patent number: 7861200
    Abstract: A method of characterizing a device under test (DUT) includes determining a goal function associated with a setup and hold time for the DUT. A minimum value for the goal function is determined by iteratively adjusting setup and hold times for input data to the DUT, and determining whether the DUT performs according to specifications. The minimum goal function value will reflect minimum setup and hold time values based on weights associated with the goal function. This allows the minimum setup and hold times for the DUT to be characterized with a small number of binary searches, improving the speed of the characterization process.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: December 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yifeng Yang, Yun Zhang, Yibin Xia, David J. Chapman
  • Patent number: 7859919
    Abstract: The present application discloses a memory array where each memory bit cell of the array includes a level shifter. In addition, each memory bit cell includes a write port that includes pass gate that can include a p-type field effect transistor and an n-type field effect transistor. The control electrodes of the p-type field effect transistor and the n-type field effect transistor are connected together as part of a common node. In addition, a current electrode of the p-type field effect transistor and a current electrode of the n-type field effect transistor are connected together to form a common node.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: December 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Louis A. De La Cruz, II, Scott I. Remington
  • Patent number: 7858505
    Abstract: A gate electrode is formed overlying a substrate. A first angled metal implant is performed at a first angle into the substrate followed by performing a second angled metal implant at a second angle. The first angled metal implant and the second angled metal implant form a first current electrode and a second current electrode. Each of the first current electrode and the second current electrode has at least two regions of differing metal composition. A metal layer is deposited overlying the gate electrode, the first current electrode and the second current electrode. The metal layer is annealed to form two Schottky junctions in each of the first current electrode and the second current electrode. The two Schottky junctions have differing barrier levels.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: December 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Byoung W. Min
  • Patent number: 7859068
    Abstract: A device (12) may have a pressure sensitive portion (17) which is protected from corrosion by a pressure transmitting material (20). Pressure transmitting material (20) may also be used to transmit pressure to pressure sensitive portion (17). A masking material (22) may be used to define an opening (26) in encapsulating material (24).
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: December 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Stephen R. Hooper, David E. Heeley
  • Publication number: 20100325327
    Abstract: A system includes a plurality of sources to provide information access requests. An arbiter includes an assignment module to associate a first access request from the first source to one of the plurality of arbitration slots based upon assignment information at a storage location, and a dispatch module to determine one request of a plurality of requests received at the plurality of sources to be dispatched to a resource, memory controller by a dispatch module.
    Type: Application
    Filed: June 17, 2009
    Publication date: December 23, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Bryan D. Marietta, Jaideep Dastidar, John Vaglica, Mihir A. Pandya
  • Publication number: 20100325481
    Abstract: A device and a method for providing core redundancy, the device includes: multiple cores; a core operability unit adapted to indicate an operability of each core out of the multiple cores; and a core control signal unit adapted to provide mapping signals that comprise virtual core to physical core mapping signals and physical core to virtual core mapping signals; wherein each core out of the multiple cores comprises at least one interrupt interface, and a crossbar interface which are responsive to at least one mapping signal.
    Type: Application
    Filed: October 20, 2006
    Publication date: December 23, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Odi Dahan, Ori Goren, Yossy Neeman
  • Patent number: 7855517
    Abstract: A current driver circuit comprises a digital circuitry having a current adjustment function and operably coupled to a current driver for providing a current to a current consuming device. The digital circuitry comprises, or is operably coupled to, a function arranged to determine a load impedance associated with the current consuming device. The current adjustment function varies a current limit applied to the current driver in response to a variation in the load impedance. In this manner, the load impedance (or temperature) of a current consuming device, such as a light bulb, is used to continuously or intermittently adjusting the current limit of a current driver circuit, such as a lamp driver, to minimize the energy dissipated in case of an overload condition.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: December 21, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Pierre Turpin, Laurent Guillot
  • Patent number: 7855581
    Abstract: Method for monitoring a real time clock and a device having real time clock monitoring capabilities, the device includes: (i) a real time clock tree, (ii) a clock frequency monitor that is adapted to determine a frequency of a real time clock signal, during a short monitoring period; (iii) a monitoring enable module, adapted to activate the clock frequency monitor during short motoring periods and to deactivate the clock frequency monitor during other periods, wherein the monitoring enable module is adapted to determine a timing of the short monitoring periods in a non-deterministic manner; and (iv) a real time clock violation indication generator adapted to indicate that a real time clock violation occurred, in response to an error signal provided from the clock frequency monitor.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: December 21, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Asaf Ashkenazi, Dan Kuzmin
  • Patent number: 7855562
    Abstract: A sensor system (20) includes transducers (32, 34) each yielding an analog signal (37, 39) representing a parameter independently sensed by each of the transducers (32, 34). The signals (37, 39) are summed and the resulting transducer signal (46) is converted to a digital transducer signal (26) by a high resolution analog-to-digital converter (ADC) (48). Concurrently, one of the signals (37, 39) is subtracted from the other. The resulting difference signal (56) is converted to a digital difference signal (60) by a low resolution ADC (58). When the digital difference signal (60) is within a threshold window (78), a fault signal (28) indicates a normal condition (80) of the transducers (32, 34). When the signal (60) falls outside of the threshold window (78), a fault signal (28) indicates a fault condition (82) of the transducers. The transducer and fault signals (26, 28) are concurrently output from the sensor system (20).
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: December 21, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Liviu Chiaburu, Marco Fuhrman, Thomas D. Ohe
  • Publication number: 20100316167
    Abstract: A clock receiver (301) on an integrated circuit (202) includes a programmable AC voltage divider (502) for receiving, through an input capacitor (406), a clock signal (206) from a clock generator (204) off the integrated circuit and for outputting a modified signal that has a reduced voltage swing, an inverter (440) coupled to the programmable voltage divider, and a common mode setting circuit (506), coupled to an input and an output of the inverter. The common mode setting circuit sets and maintains a common mode at the input of the inverter in response to a voltage at the input of the inverter and a voltage at the output of the inverter. The strength of transistors in the common mode tracking circuit tracks the strength of transistors in the inverter such that the common mode at the input to the inverter tracks a trip point of the inverter.
    Type: Application
    Filed: June 15, 2009
    Publication date: December 16, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Xinghai TANG, Hector SANCHEZ
  • Publication number: 20100314769
    Abstract: An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterised in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.
    Type: Application
    Filed: September 20, 2007
    Publication date: December 16, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Greg Braeckelmann, Hisao Kawasaki, Marius Orlowski, Emmanuel Petitprez
  • Publication number: 20100318713
    Abstract: Flow control mechanisms avoid or eliminate retries of transactions in a coherency interconnect. A class of transaction (CoT) framework is defined whereby individual transactions are associated with CoT labels consistent with chains of dependencies that exist between transactions initiated by any of the cooperating devices that participate in a given operation. In general, coherency protocols create dependencies that, when mapped to physical resources, can result in cycles in a graph of dependencies and deadlock. To support architectural mechanisms for deadlock avoidance, CoT labels are applied to individual transactions consistent with a precedence order of those transactions both (i) with respect to the operations of which such transactions are constituent parts and (ii) as amongst the set of such operations supported in the coherency interconnect.
    Type: Application
    Filed: June 16, 2009
    Publication date: December 16, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Sanjay Deshpande
  • Patent number: 7852811
    Abstract: In a collaborative, multiple input, multiple output wireless communication system, a transmitting device transmits a peak-limited pilot signal to a receiving device. The receiving device independently synthesizes the same pilot signal transmitted by the transmitting device. The synthesis process involves precoding the pilot signal and peak limiting the precoded pilot signal. The receiving device receives a signal r that represents the product of (i) a channel matrix H between the transmitting device and the receiving device and (ii) the peak-limited pilot signal yp(n)? plus noise ?, i.e. r=Hyp(n)?+?. The synthesized, peak-limited pilot signal can then be used by a channel estimator to determine an estimated channel matrix ?. Thus, the estimated channel matrix ? represents a closer estimate of the channel matrix H than conventional channel estimation processes and, thus, can provide better corresponding performance than conventional MIMO wireless communication systems.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: December 14, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: James W. McCoy
  • Patent number: 7851889
    Abstract: Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the surface, and the transistor source includes an area (310) of alternating conductivity regions (3110, 3120). Another apparatus includes a semiconductor body (120) including a first conductivity and a transistor source (500) located in the semiconductor body. The transistor source includes multiple regions (5120) including a second conductivity, wherein the regions and the semiconductor body form an area (510) of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well (120) including a first conductivity in a substrate (110) and implanting a plurality of doped regions (5120) comprising a second conductivity in the semiconductor well.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: December 14, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ronghua Zhu, Amitava Bose, Vishnu K. Khemka, Todd C. Roggenbauer
  • Patent number: 7852915
    Abstract: Adaptive equalizers for a communication channel and corresponding methods of equalizing are described. The adaptive equalizer includes: a fixed pre-filter configured to be coupled to a received signal and provide a pre-filter signal; an adaptive filter coupled to and configured to compensate the pre-filter signal for changes in phase and amplitude; and an interference remover coupled to the adaptive filter and configured to reduce interference in the received signal.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: December 14, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Weizhong Chen