Abstract: A method of generating a frame of audio data for an audio signal from preceding audio data for the audio signal that precede the frame of audio data, the method comprising the steps of: predicting a predetermined number of data samples for the frame of audio data based on the preceding audio data, to form predicted data samples; identifying a section of the preceding audio data for use in generating the frame of audio data; and forming the audio data of the frame of audio data as a repetition (602) of at least part of the identified section to span the frame of audio data, wherein the beginning of the frame of audio data comprises a combination of a subset of the repetition (602) of the at least part of the identified section and the predicted data samples.

Abstract: Improved Schottky diodes (20, 20?) with reduced leakage current and improved breakdown voltage are provided by building a JFET with its current path (50, 50?) of a first conductivity type serially located between a first terminal (80, 80?, 32, 32?) comprising a Schottky contact (33, 33?) and a second (82, 82?, 212, 212?) terminal. The current path (50, 50?) lies (i) between multiple substantially parallel finger regions (36, 36?) of a second, opposite, conductivity type substantially laterally outboard of the Schottky contact (33, 33?), and (ii) partly above a buried region (44, 44?) of the second conductivity type that underlies a portion (46, 46?) of the current path (50, 50?), which regions (36, 36?; 44, 44?) are electrically coupled to the first terminal (80, 80?, 32, 32?) and the Schottky contact (33, 33?) and which portion (46, 46?) is electrically coupled to the second terminal (82, 82?, 212, 212?).

Abstract: A secure real time clock (RTC) system is provided, comprising a secure RTC, a frequency signal generator, and a frequency adjuster connected between the secure RTC and the frequency signal generator to receive a signal having a first frequency from the frequency signal generator. On receipt of a first control signal the frequency adjuster outputs the signal having the first frequency to the secure RTC, and on receipt of a second control signal the frequency adjuster adjusts the signal having the first frequency to generate a signal having a second frequency, the second frequency being lower than the first frequency, and outputs the signal having the second frequency to the secure RTC.

Abstract: An audio amplifier includes an output stage for generating an output stage voltage in response to an input signal and an output stage quiescent current. A controlled current source controls the output stage quiescent current in response to a quiescent current signal during a start-up cycle.

Abstract: A pulse width modulation (PWM) signal generator generates multiple output PWM signals from an input PWM signal, whereby each output PWM signal has a frequency and duty ratio substantially similar to the input PWM signal and each output PWM signal is phase-shifted in relation to the other output PWM signals. The PWM signal generator samples a PWM cycle of the input PWM signal to determine various PWM parameters representative of the duration of the active portion of the sampled PWM cycle and the total duration of the sampled PWM cycle. The PWM signal generator then uses the PWM parameters to generate corresponding PWM cycles for the output PWM signals using a set of two independent counters. This process of sampling a PWM cycle of the input PWM signal and generating the output PWM signals based on the PWM parameters resulting from the sampling process can be repeated for one or more iterations.

Abstract: A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.

Abstract: In a method for measuring round trip time (RTT), an RTT measurement packet is transmitted to a destination node. The RTT from transmission of the RTT measurement packet to reception of a response from the destination node is measured to determine if the RTT is greater than a predetermined time period. If the RTT is greater than the predetermined time period, an RTT measurement packet is repeatedly retransmitted at a different time interval and the RTT is remeasured until either the RTT measurement packet has been transmitted a predetermined number of times or the RTT is not greater than the predetermined time period.

Abstract: A processor-implemented method for making a semiconductor device having a test logic block and a functional logic block is provided. The method includes retrieving hardware description for at least one test logic block and mapping the hardware description for the at least one test logic block to logic gates to generate at least one synthesized test logic block. The method further comprises retrieving hardware description for at least one functional logic block and mapping the hardware description for the at least one functional logic block to logic gates to generate at least one synthesized functional logic block. The method further includes merging the at least one synthesized test logic block with the at least one synthesized functional logic block when the at least one functional logic block meets at least one criterion for selection as a candidate for merger with the at least one test logic block.

Abstract: A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.

Abstract: A method including performing a program/erase cycle on a first non-volatile memory (NVM) bit of an integrated circuit using a first fluence, wherein the first NVM bit has a first transconductance is provided. The method further includes performing a program/erase cycle on a second NVM bit of the integrated circuit using a second fluence, wherein the second NVM bit has a second transconductance, and wherein the first transconductance is greater than the second transconductance and the second fluence is greater than the first fluence.

Abstract: In one embodiment, a tone event detector first determines whether the presence of a tone is indicated on the input signal, and then, based on this determination, selectively determines whether a tone has been detected on the input signal. For example, in one embodiment, tone detection is performed only when the presence of a tone is first indicated, such that if the presence of a tone is not indicated, tone detection need not be performed. This may help reduce complexity of a tone event detector since a simplified method may be used to indicate the presence of a tone, and the more complex algorithms for tone detection may be enabled only when needed. Also, in one embodiment, detection of a tone includes generating one or more tone characteristics corresponding to the detected tone which may then be used to determine whether the detected tone corresponds to a valid tone event.

Abstract: A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latch (540) generates a flip flop output signal at a launch time under control of a slave clock signal, clock generation circuitry (550) generates a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode, and data propagation logic circuitry (564) uses the first and second clock signals to generate the master and slave clock signals during a scan mode to delay the launch time of the slave latch with respect to the hold time of the master latch.

Abstract: An integrated circuit (IC) module (20) includes a ground plane (22) having adjoining cutouts (30, 32). The cutout (32) defines a critical signal pathway (38). A device (24) is positioned in the cutout (30) and a device (26) is positioned outside of the cutout (30) adjacent to the cutout (32). An electrical interconnect (56) positioned in the critical signal pathway (38) interconnects the device (24) with the device (26). A method (60) of packaging the IC module (20) entails encapsulating the ground plane (22) and devices (24, 26) in a packaging material, and forming conductive vias (92) in the packaging material (84) that extend between the ground plane (22) and an exterior surface (94) of the packaging material (84). The conductive vias (92) surround the device (24) and cutout (32) to protect again electromagnetic interference and to provide guided signal pathways for high frequency signals on electrical interconnect (56).

Abstract: An integrated circuit pad structure includes a ground strip (206) positioned below a pad (101). In one example a conductive element (102) is coupled to the pad (101), and at least two tiled layers, positioned below the first conductive element (102) and positioned above the ground strip (206) are included. A conductor (203), may run beneath the ground strip (206). In a second example, a pad (101) is seated on a ground shield cage having a bottom conductive ground element (302) including several ground strips where at least one ground strip (116) is along a signal routing path. The ground shield cage further includes a set of stacked conductive ground elements, stacked to form sidewalls (209, 210) of the cage. The top conductive ground element (301) of the stacked elements has an inner perimeter and an outer perimeter, such that the inner perimeter surrounds the pad (101) and the top conductive ground element (301) is in the plane of the conductive element (102) coupled to the pad (101).

Abstract: An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

Abstract: A temperature-compensated voltage comparator (301) that compares first and second input voltages includes first and second bipolar junction transistors (BJTs) (221 and 222) that convert the first and second input voltages to first and second input currents, respectively. The first and second BJTs share a same thermal environment and their currents are dependent upon temperature. A temperature-compensating circuit (350), which includes a zero thermal coefficient reference (419), generates a logarithmic temperature-compensating factor that compensates for temperature dependency of the first and second BJTs. The temperature-compensating circuit receives one of the input currents, and outputs a temperature-compensated current that is said input current multiplied by the logarithmic temperature-compensating factor. The temperature-compensating circuit shares a thermal environment with the first and second BJTs.

Abstract: Field effect devices and ICs (80, 82, 84) with very low gate-drain capacitance Cgd are provided by forming a substantially empty void (70, 100) between the gate (60?) and the drain (27) regions. For vertical FETS a cavity (70, 100) is etched in the semiconductor (SC) (40) and provided with a gate dielectric liner (54, 92). A poly-SC gate (60?) deposited in the cavity (50) has a central fissure (empty pipe) (63) extending through to the underlying SC (40). This fissure (63) is used to etch the void (70, 100) in the SC (40) beneath the poly-gate (60?). The fissure (63) is then closed by a dielectric plug (74, 84, 102) formed by deposition or oxidation without significantly filling the etched void (70, 100). Conventional process steps are used to provide the source (24) and body regions (25) around the cavity (50) containing the gate (60?), and to provide a drift space (26) and drain region (27) below the body region (25).

Abstract: An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.

Abstract: Method (200) and apparatus (30, 50-53) are described for MOS capacitors (MOS CAPs). The apparatus (30, 50-53) comprises a substrate (31) having Ohmically coupled N and P semiconductor regions (32, 34; 54, 56; 92, 94) covered by a dielectric (35, 57, 95). A conductive electrode (36, 58, 96) overlies the dielectric (35, 57, 95) above these N and P regions (32, 34; 54, 56; 92, 94). Use of the Ohmically coupled N and P regions (32, 34; 54, 56; 92, 94) substantially reduces the variation (40, 64, 70, 80) of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions (32, 34; 54, 56; 92, 94) have unequal doping, the capacitance variation (40, 64, 70, 80) may still be substantially compensated by adjusting the properties of the dielectric (57, 95) above the N and P regions (54, 56; 92, 94) and/or relative areas of the N and P regions (54, 56; 92, 94) or both.

Abstract: A method and system for decoding a received data stream are disclosed. The appropriate time interval to decode the received data stream is derived from the data stream itself. A header of the data stream is analyzed to determine two sets of time ranges, each set of time ranges corresponding to a set of possible data transmission intervals. A preamble of the header contains timing information for development of a first set of time ranges to decode a synchronization word of the header. The synchronization word contains both data information and timing information to develop the second set of time ranges. The data information included in the header is used validate the data stream for the receiving device. The second set of time ranges is used to decode a data payload portion of the data stream.