Abstract: A device having an OTP memory is disclosed. A program state of the OTP device is stored at a fuse that is connected in series between a first node and a latch. During a program mode, the first node is electrically connected to a program voltage. During a read mode, the first node is electrically connected to ground, whereby a first divided voltage is generated at a first node of the latch.

Abstract: A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.

Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

Abstract: A method for forming a dielectric layer is disclosed herein. In accordance with the method, a first material is provided (303) which comprises a suspension of nanoparticles in a liquid medium. A dielectric layer is then formed (305) on the substrate from the suspension through an evaporative process.

Abstract: A method is provided for sending ultrawide bandwidth signals from first and second wireless networks across an available wireless bandwidth. This method can provide a gap in the available bandwidth to reduce interference with other devices that might use the frequencies in that gap. This is useful in ultrawide bandwidth implementations to avoid interference with devices in the UNII band. The available wireless bandwidth is divided into high and low bands, and each of these bands can be used by a different overlapping network. By adjusting the center frequencies and the 3 dB bandwidths of the high and low bands, the size and placement of the gap can be determined.

Abstract: A method is provided for performing a clear channel assessment in a wireless network. The method involves first listening for channel energy on a wireless channel. Whatever channel energy is heard over the wireless channel is demodulated into non-synchronized in-phase and non-synchronized quadrature phase components. Each of the non-synchronized in-phase and non-synchronized quadrature phase components are squared, and then the non-synchronized in-phase component is multiplied by the non-synchronized quadrature phase component to produce an I?Q product. The sum of the squared non-synchronized in-phase component, the inverse of the squared non-synchronized quadrature component, and double the I?Q product is determined as a clear channel assessment input value. A carrier signal detection function is then performed on the clear channel assessment input value to produce a clear channel assessment output value, which is used to determine whether a signal is present in the wireless channel.

Abstract: A charge pump system has a charge pump for receiving a clock signal and provides an output signal of increased voltage magnitude in response to an enable signal. A plurality of comparators is coupled to the charge pump for detecting when the output signal is greater than a reference value. Each of the plurality of comparators is controlled by a respective different control signal derived from the clock signal and has differing phases. Detection circuitry is coupled to the plurality of comparators for providing the enable signal in response to detecting first leading rising edges and first leading falling edges of signals provided by the plurality of comparators. The interleaving operation of the comparators results in tighter regulation of the charge pump which reduces voltage ripple without significantly increasing capacitive load on the charge pump.

Abstract: A voltage controlled oscillator (VCO) has a plurality of series-connected inverters. Within each inverter a first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

Abstract: A method is provided for a remote device to monitor and communicate with a wireless network using cyclic beacons. The remote device receives a beacon, which beacon includes beacon information that defines a superframe. From the beacon information, the remote device determines whether the received beacon and the associated superframe are assigned to a network device or are unassigned. By receiving as many beacons as there are allowable devices in the network, the remote device can determine if the network is full. If the remote device runs through all of the beacons and all indicate that their associated superframes are assigned, then the remote device determines that the network is full and performs a network-full function. If the remote device receives a beacon that indicates that its associated superframe is unassigned, it determines that the network is not full and performs an association request during the unassigned superframe.

Abstract: A method for forming multi-layer bumps on a substrate includes depositing a first metal powder on the substrate, and selectively melting or reflowing a portion of the first metal powder to form first bumps. A second metal powder is then deposited on the first bumps, and melted to form second bumps on the first bumps. A masking plate is disposed over the substrate to select the portions of the metal powders that are melted and the metal powders are melted via an irradiation beam. The multi-layer bump is formed without the need for any wet chemicals.

Abstract: An ultra wide bandwidth, high speed, spread spectrum communications system uses short wavelets of electromagnetic energy to transmit information through objects such as walls or earth. The communication system uses baseband codes formed from time shifted and inverted wavelets to encode data on a RF signal. Typical wavelet pulse durations are on the order of 100 to 1000 picoseconds with a bandwidth of approximately 8 GHz to 1 GHz, respectively. The combination of short duration wavelets and encoding techniques are used to spread the signal energy over a an ultra wide frequency band such that the energy is not concentrated in any particular narrow band (e.g. VHF: 30-300 MHz or UHF: 300-1000 MHz) and is not detected by conventional narrow band receivers so it does not interfere with those communication systems.

Abstract: A method of testing for power and ground continuity of a semiconductor device having Input and Output (IO) pins and at least a pair of power and ground pins includes identifying the power and ground pins of the device. A victim pin is selected from the IO pins of the device for each pair of the power and ground pins, and an aggressor pin for each victim pin is selected from the remaining IO pins. The aggressor pins are toggled between a high state and a low state. A level of switching noise on each victim pin is measured, and the measured levels of switching noise are compared with predetermined data to determine power and ground continuity of the device.

Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.

Abstract: A method of determining a synchronous phase includes receiving a correlation sequence, and selecting one or more correlated signals from the correlation sequence. Then, when the number of selected correlated signals is odd, the synchronous phase corresponding to a central correlated signal is selected.

Abstract: A wireless communication device, an individual information writing device, and an individual information setting method that efficiently write individual information, such as a unique identifier used for wireless communication, to each wireless device. An address writing device transmits a unique address setting communication request. A wireless device has a control unit that checks whether a provisional address is set in a unique address memory. When a provisional address is set, the control unit measures the signal intensity of a received unique address setting communication request with an electric field intensity measuring unit. When the electric field intensity is greater than a threshold value stored in an address setting condition memory and thereby satisfies an address setting condition, the wireless device performs a process for setting a unique address and then transmits a completion notification to the address writing device.

Abstract: A method includes generating an instruction address value in response to an instruction source event. The method further includes selectively generating a breakpoint request based on the instruction source event and responsive to a comparison of the instruction address value to a breakpoint address value. In one embodiment, selectively generating a breakpoint request includes comparing the instruction source event to an instruction source event type, comparing the instruction address value to a breakpoint address value, and generating the breakpoint request responsive to a match between the first instruction source event type and the instruction source event and a match between the instruction address value and the breakpoint address value.

Abstract: A method of forming a semiconductor component (100) having an active semiconductor device (680) above a passive device (470) includes providing a semiconductor wafer (110) having an upper surface (115), forming a trench (216) in the upper surface of the semiconductor wafer, forming a cavity (317) in the semiconductor wafer below the trench, forming the passive device in the cavity; and forming at least a portion of the active semiconductor device in the semiconductor wafer and above the passive device.

Abstract: Current is provided from a first node coupled to an output of a power supply to a second node coupled to a voltage supply input of an electronic device under test via a transistor having a first current-carrying electrode coupled to the first node and a second current-carrying electrode coupled to the second node. A first voltage is determined based on a voltage difference between the first node and the second node and a second voltage is determined based on a comparison of the first voltage to a voltage of the second node. The transistor is selectively disabled based on the second voltage.

Abstract: A device for error correction and methods thereof are disclosed. The method includes retrieving raw data from a memory device during a first operational phase of the error correction device. The raw data is retrieved by a bus interface device that interfaces with a variety of memory devices. During a second operational phase, the raw data is outputted from the bus interface device to the bus master. In addition, error correction data is calculated, and error correction is performed on the raw data during the second operational phase. By retrieving the raw data before performing error correction, and by outputting the raw data and correction the raw data during the same operational phase, data may be retrieved from the memory more rapidly.

Abstract: A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semiconductor active layer and a stressor material is deposited on a bottom of the first trench, wherein the stressor material includes a dual-use film. A second isolation trench is formed within the semiconductor active layer, wherein the second isolation trench is absent of the stressor material on a bottom of the second trench. The presence and absence of stressor material in the first and second isolation trenches, respectively, provides differential stress: (i) on one or more of N-type or P-type devices of the semiconductor device structure, (ii) for one or more of width direction or channel direction orientations, and (iii) to customize stress benefits of one or more of a <100> or <110> semiconductor-on-insulator substrate.