Abstract: A system for distributing an available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage. The system may further comprise bus access ports which support at least one of concurrent access by a bus access port to access redundantly stored data or non-redundantly stored data, or concurrent access by at least two bus access ports to respective RAM elements to access redundantly stored data or to a respective one of the RAM elements to access non-redundantly stored data. Comparison logic and error detection or correction logic may be provided to detect or correct errors in information read from the RAM elements.

Abstract: An apparatus for controlling a charge pump includes a current sensor arranged to output a current sense signal that is linearly proportional to an output current of the charge pump, and an oscillator that provides a clock signal for the charge pump. The oscillator receives the current sense signal and uses it to vary an oscillation frequency of the clock signal. An amplitude of the clock signal also may be varied in response to the current sense signal.

Abstract: A circuit device mounted on a substrate includes a detection circuit that monitors a characteristic of a return signal to determine an integrity of various interconnects of the device.

Abstract: A communication unit comprises a power DAC. The DAC comprises: a switched mode power amplifier (SMPA); and a digital band-pass sigma-delta modulator operably coupled to the SMPA. The sigma-delta modulator comprises an input to receive an input baseband signal; a delay; an adder module arranged to add a feedback signal with an output from the delay; and at least two feedback branches. The sigma-delta modulator is arranged to digitally oversample the input baseband signal such that a ratio of a sampling frequency employed by the sigma-delta modulator to a radio frequency (RF) output from the DAC is fixed and the sampling frequency tuned or wherein the sampling frequency is fixed and the ratio is adjusted, such that a first feedback branch in the sigma-delta modulator is formed using at least one from a group of: a zero gain, an additive inverse of a second feedback branch.

Abstract: The present invention relates to a circuit arrangement for processing a digital video stream, the circuit arrangement comprising: an input interface for receiving a digital video stream, a processing circuit which is arranged to process the digital video stream, a hang-up detecting circuit for detecting a fault in the processed digital video stream, the hang-up detecting circuit comprising: a checksum generating circuit which is arranged to generate checksums for the frames of the processed digital video stream, a memory for storing generated checksums and an analyzing device arranged to compare a currently generated checksum to a plurality of corresponding checksums of preceding frames stored in the memory and to generate an error signal if at least one predefined amount of compared checksums are matching. The present invention also relates to a digital video system, a method for processing a digital video stream and a computer readable program product.

Abstract: A converter unit for an M-order digital modulation to map L input binary sequences of N bits onto M complex values being transmitted through a communication channel, where M=2N and L and N are positive integers. The converter unit comprises an input to receive a respective input binary sequence. The converter unit is arranged to individually convert each N bits of the input binary sequence into a real number to obtain a sequence with N real numbers. The converter unit is arranged to execute complex arithmetic operations on the sequence of real numbers and to compute a respective complex value. The respective complex value corresponds to said respective input binary sequence.

Abstract: The invention relates to a network processor for managing communication between a central processing unit running tasks on one or more partitions, and a PPA logic circuitry. Management portals pass messages to and from the central processing unit. A management portal communicates with one of the partitions. A resource state manager is arranged to manage resources of the PPA logic circuitry and to communicate states of the resources to the tasks via the management portals. A controller driver drives the PPA logic circuitry using information received from the resource state manager and the instructions from a data interface. The networking device does not need a separate master partition, and is allowing a programmer to deploy the system fast and with minimal risk or effort on different integrated systems.

Abstract: A start-up method for a self-powered gate drive circuit driving a power transistor gate. The method comprises charging, with a single-supply voltage, a first supply capacitor of a first gate drive circuit; switching on a first power transistor by applying a current supplied by a discharge of the first supply capacitor of the first gate drive circuit to the gate of the first power transistor; charging a second supply capacitor of the first gate drive circuit using an output signal from the first power transistor; and re-charging the first supply capacitor by applying a current supplied by a discharge of the second supply capacitor to the first capacitor.

Abstract: A method of testing a semiconductor device against electrostatic discharge includes operating the semiconductor device, and, while operating the semiconductor device, monitoring a functional performance of the semiconductor device. The monitoring includes monitoring one or more signal waveforms of respective one or more signals on respective one or more pins of the semiconductor device to obtain one or more monitor waveforms, and monitoring one or more register values of one or more registers of the semiconductor device to obtain one or more monitor register values as function of time. The method includes applying an electrostatic discharge event to the semiconductor device while monitoring the functional performance of the semiconductor device. The method can further comprise determining a functional change from the one or more monitor waveforms and the one or more monitor register values as function of time.

Abstract: An integrated circuit electrical protection device is disclosed that includes a semiconductor substrate and a plurality of transistor fingers partitioned into a plurality of segments. The segments are distinguished from one another by well-ties spaced apart from each other within a source/drain region that is shared by adjacent segments.

Abstract: A self-powered gate drive circuit comprising a first capacitor electrically coupled to a power semiconductor collector node of the circuit; a first switch arranged between the first capacitor and a second capacitor, the first switch electrically coupling the first and second capacitors when switched on; the second capacitor; a first diode, the first diode anode electrically coupled to the first capacitor and the first diode cathode electrically coupled to the first switch; a second diode, the second diode cathode electrically coupled to the first capacitor and the second diode anode electrically coupled with a ground node of the circuit; and a second switch, wherein the second switch electrically couples the second capacitor with a power semiconductor gate node when switched on.

Abstract: A method of performing state retention, for example during power gating, for at least one functional block within an integrated circuit device. The method comprises enabling at least one scan chain within the at least one functional block, scanning out a set of scan chain values from the at least one scan chain, a subset of the set of scan chain values comprising validation values, and writing the set of scan chain values to at least one memory element. The method further comprises retrieving the set of scan chain values from the at least one memory element, and validating the validation values within the retrieved set of scan chain values.

Abstract: A current sensor comprises a current carrying trace located within a substrate; and a sensing trace located within the substrate proximate to the current carrying trace; wherein the sensing trace detects an electromagnetic force (emf) generated by magnetic flux inductively coupled from the current carrying trace for transmitting to a current sensing device.

Abstract: A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The hardware module stores a first ordering scope identifier at a first storage location of the ordering scope manager. The first ordering scope identifier indicates a first ordering scope that a first task is operating in. The ordering scope manager increments the first ordering scope identifier to create a new ordering scope identifier. In response to determining that the processor core is authorized to transition the first task from the first ordering scope to a second ordering scope associated with the new ordering scope identifier, the ordering scope manager provides hint information to the processor core. The processor core transitions from the first ordering scope to the second ordering scope without completing a task switch in response to the hint information.

Abstract: A digital device includes one or more requestor units, one or more responder units, and a bus. Each responder unit is connected to the requestor units via the bus and includes a plurality of responder elements which are accessible by the requestor units via the bus and which include one or more critical responder elements. The digital device further includes one or more wrapper units. Each wrapper unit includes an interface unit arranged to enable the requestor units to access the responder elements of the respective responder unit associated with the respective wrapper unit and a checksum unit arranged to respond to any write access to any one of the critical responder elements by computing and storing a reference checksum. The checksum unit is arranged to compute the reference checksum by applying a checksum algorithm to a subset of the critical responder elements, including at least the write-accessed critical responder element.

Abstract: A data processing system includes a processor core and ordering scope manager circuitry. The processor core sends an indication of a first ordering scope identifier for a current ordering scope a task currently being executed by the processor core and a second ordering scope identifier for a next-in-order ordering scope of the task. The ordering scope manager receives the indication the first and second ordering scope identifiers from processor core, and, provides a no task switch indicator to the processor core in response to determining that the first task is a first-in-transition-order task for the first ordering scope identifier and that processor core is authorized to execute the next-in-order ordering scope. The processor core transitions from executing in the current ordering scope to executing in the next-in-order ordering scope without performing task switch in response to the no task switch indicator being provided.

Abstract: An integrated circuit (IC) with voltage regulation includes high power and low power domains, low and high voltage regulators and a low power regulator. The low voltage regulator powers the high and low power domains when the IC is in a HIGH power mode. The low power regulator receives a voltage from a high voltage regulator and powers the low power domain when the IC is in a LOW power mode. The IC includes a switching module that disconnects the low voltage regulator from the low power domain when the output voltage of the high voltage regulator is lower than a threshold voltage during power-up and connects the low voltage regulator to the low power domain when the voltage regulated by the high voltage regulator exceeds the threshold voltage.

Abstract: An airbag apparatus connected with a battery includes activation circuits each of which has a squib and a high-side switching element, a safing switching element connected between the battery and the activation circuits, a safing switch control circuit controlling the safing switching element to provide a target voltage to the activation circuits, a terminal voltage acquiring circuit that acquires a terminal voltage of each squib, and a target voltage setting circuit that sets the target voltage. When a maximum-terminal voltage is lower than a reference voltage, the target voltage setting circuit sets the target voltage to be equal to the reference voltage. When the maximum-terminal voltage is higher than the reference voltage, the target voltage setting circuit sets the target voltage to correspond to the maximum-terminal voltage so that a reverse current is avoided in the high-side switching element.

Abstract: Apparatus for and a method of decompression of block coded video data in a multi-core processor. The processor cores decode respective coded groups of blocks of video data independently, in parallel and deblock respective decoded groups of blocks of video data independently and in parallel with the decode operations and with other deblock operations.

Abstract: A shielding structure for use with semiconductor devices. The shielding structure has a base with fingers that are sized and shaped to extend within the space between pairs of adjacent leads. The base extends within the space between the die flag and the leads. The shielding structure is further connected to one of the grounded leads.