Patents Assigned to Freescale
  • Collapsible Probe Tower Device and Method of Forming Thereof
    Publication number: 20150287654
    Abstract: A collapsible probe tower device and methods of forming thereof, are disclosed. In one example embodiment, a method of forming a device includes providing a semiconductor die substrate having a contact pad and a probe pad, wherein the contact pad and probe pad are adhered to the substrate, forming a contact bump by applying a conductive material to a contact structure surface of a contact tower, wherein the contact tower includes the contact pad, forming a probe bump by applying a conductive material to a probe structure surface of a probe tower, wherein the probe tower includes the probe pad, and heating the conductive material that forms the contact bump and the probe bump to provide a first reflow, wherein after the first reflow, the height of a top surface of the probe bump exceeds the height of a top surface of the contact bump.
    Type: Application
    Filed: April 7, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Trent S. Uehling, Kelly F. Folts
  • SEMICONDUCTOR WAFER AND METHOD OF CONCURRENTLY TESTING CIRCUITS FORMED THEREON
    Publication number: 20150287656
    Abstract: A semiconductor wafer has an array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring. Each die has a group of bond pads and test pads coupled to the bond pads. A test pad region is formed on the wafer. The test pad region has probe pads and common electrical interconnects that selectively electrically couple each of the probe pads to a bond pad on each of the dies. The common electrical interconnects in the test pad region reduce the possibility of probe damage to the integrated circuits and allow the dies to be tested concurrently before being cut from the wafer.
    Type: Application
    Filed: May 28, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Dewey Killingsworth
  • Test Mode Entry Interlock
    Publication number: 20150285858
    Abstract: An integrated circuit haying normal and special operating modes includes a mode entry interlock (201) which is enabled by an initialization command and an externally supplied voltage at a first I/O terminal (204) to detect a conflict at the I/O terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second I/O terminal (212) for receiving a disassociated software command to enter into the special operating mode, and mode control logic (210, 216) for evaluating the received software command against any detected conflict at the I/O terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state.
    Type: Application
    Filed: April 2, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: William E. Edwards, John M. Hall
  • Solder Pad for Semiconductor Device Package
    Publication number: 20150287685
    Abstract: A solder ball pad for mounting a solder ball of a semiconductor device for preventing delamination of an overlying dielectric layer, and particularly devices and methods providing improved solder ball pad structures in a device such as a semiconductor device package.
    Type: Application
    Filed: April 2, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Vijay Sarihan, Zhiwei Gong, Scott M. Hayes
  • METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR MEASURING USER PERCEPTION QUALITY OF A PROCESSING SYSTEM COMPRISING A USER INTERFACE
    Publication number: 20150286551
    Abstract: A method for measuring user perception quality of a processing system comprising a user interface is presented. The method comprises measuring a first processing time for processing, by the processing system, one or more times one or more operations in a batch mode; measuring a second processing time for processing, by the processing system, the one or more times the one or more operations and a predefined safety period in a user mode; and determining a user perception metric as a difference of a first value and a second value, the first value being determined depending on a ratio of the second processing time and the first processing time, the second value being determined depending on a ratio of the predefined safety period and the first processing time.
    Type: Application
    Filed: December 6, 2011
    Publication date: October 8, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Cristian Tepus
  • TAMPER DETECTOR POWER SUPPLY WITH WAKE-UP
    Publication number: 20150286846
    Abstract: A tamper detector has tamper detection logic connected to tamper detection ports through a tamper detection interface. A real-time clock (RTC) provides a clock signal and has a battery. A processor is powered by an external power supply in a powered operational mode and has a power-off mode. In a wake-up configuration, a wake-up signal on a specific I/O port awakens the external power supply from the power-off mode to supply power to the RTC and the tamper detection interface when power from the battery is unavailable. The tamper detection ports continue to function despite removal or discharge of the battery without ESD concerns. The specific I/O port optionally may be configured for passive tamper detection.
    Type: Application
    Filed: April 6, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Siddi Jai Prakash, Kumar Abhishek, Prashant Bhargava, Michael A. Stockinger
  • CAVITY-DOWN PRESSURE SENSOR DEVICE
    Publication number: 20150285702
    Abstract: A cavity-down pressure sensor device has a pressure-sensing die that is electrically connected to a master control unit (MCU) using face-to-face bonding. Connecting the pressure-sensing die in this manner avoids the need to wire bond the pressure-sensing die to the master control unit.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Wai Yew Lo
  • INTEGRATED CIRCUIT WITH LBIST SUB-PARTITIONS
    Publication number: 20150285859
    Abstract: A Logic Built-In Self-Test (LBIST) domain of an integrated circuit is divided into partitions that in turn are subdivided into sub-partitions. Each sub-partition has an associated clock gating logic circuit that enables or inhibits the clock signal supplied to scan chains within the sub-partition. A user-defined number of sub-partitions, which can be specified on the basis of silicon results and power requirements of the integrated circuit, may be activated at any one time during a portion of an LBIST execution, which reduces toggling of concurrent scan chains, resulting in a reduction of energy consumption during testing, and reduces voltage droop due to inertia of power management control modules at the start of an LBIST test.
    Type: Application
    Filed: April 6, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Reecha Jajodia, Gagan Anand, Anurag Jindal
  • CLOCK DISTRIBUTION ARCHITECTURE FOR INTEGRATED CIRCUIT
    Publication number: 20150288366
    Abstract: An integrated circuit (IC) includes multiple circuit modules that have specific clocking requirements, multiple clock sources (e.g., PLLs, duty cycle re-shaper, etc.), and at least one clock input port. The clock sources have specific clock source specifications, and the circuit modules have specific clocking requirements. The clock sources are selected based on an identification of the most common clocking requirements, and then placed at routing distances measured from the input port that are less than corresponding predetermined maximum routing distances such that the clocking requirements of the circuit modules are met. The IC thus generates clock signals internally, rather than externally.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Amit Aggarwal, Himanshu Goel, Ashish Malhotra, Ankit Pal
  • SEMICONDUCTOR WAFER AND METHOD OF CONCURRENTLY TESTING CIRCUITS FORMED THEREON
    Publication number: 20150287655
    Abstract: A semiconductor wafer has a non-uniform array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring, and each die has a group of bond pads and probe pad coupled to the bond pads. Common electrical interconnects selectively electrically couple together respective probe pads of each of the dies. The common electrical interconnects allow the dies to be tested concurrently before being cut from the wafer.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Dewey Killingsworth
  • DEFECTIVE DIE REPLACEMENT IN A DIE STACK
    Publication number: 20150287653
    Abstract: The dies of a stacked die IC are tested and, in response to detection of a defect at one of the dies, the type of defect is identified. If the defect is identified as a defective module repairable at the die itself, a redundant module of the die is used to replace the functionality of the defective module. If the defect is identified as one that is not repairable, a replacement die in the die stack is used to replace the functionality of the defective die.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Perry H. Pelley, Michael B. McShane, Tim V. Pham
  • METHOD AND APPARATUS FOR DRIVING A POWER TRANSISTOR GATE
    Publication number: 20150288356
    Abstract: A gate drive circuit includes a first switch electrically coupled to a single-supply input voltage node, the first switch electrically coupling the voltage node with a first capacitor if switched on; a second switch electrically coupled to a ground node, the second switch electrically coupling the first capacitor with the ground node if switched on; and the first capacitor. A first capacitor lead of the first capacitor is electrically coupled to the first and second switches and a second capacitor lead of the first capacitor is arranged to connect with a power transistor gate.
    Type: Application
    Filed: October 31, 2012
    Publication date: October 8, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Thierry Sicard, Philippe Perruchoud
  • Backscattering for localized annealing
    Patent number: 9153644
    Abstract: A method of fabricating an electronic apparatus includes forming an active layer over a wafer, forming a backscatter layer over the wafer, and directing radiation toward the wafer to anneal the active layer. The backscatter layer is not transparent to the radiation, more reflective than absorptive of the radiation, and positioned such that the backscatter layer inhibits exposure of the wafer to the radiation apart from the active layer.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: October 6, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Nirmal David Theodore
  • Power adapter and electrical connector therefor
    Patent number: 9152198
    Abstract: A power adapter and an electrical connector for the power adapter operate to provide power to an electronic device such as a laptop computer. The power adapter includes a switch and a circuit for detecting whether or not the electrical connector is connected to the electronic device. If the adapter is not connected to an electronic device, the switch is opened so that no power is drawn from an AC supply. The electrical connector includes first and second conductors that are electrically connected to the detection circuit. The detection circuit detects a change in potential when the connector is plugged into an electronic device.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: October 6, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Changhao Shi, Yu Wen, Jianxin Zhang
  • Spare gate cell for integrated circuit
    Patent number: 9154135
    Abstract: Spare gate cells for inclusion in an integrated circuit have multiple inputs and outputs and are capable of selectively performing, concurrently, multiple logic functions on signals appearing at the inputs. Selection of required logic functions depends on the connections of at least one of the inputs of the spare cell. One of the outputs is fed back to an input of the spare gate cell to provide certain functionality while other outputs are set to a fixed logical value. The spare gate cell may be configured to perform NOR, OR and inverter operations on inputs simultaneously.
    Type: Grant
    Filed: April 27, 2014
    Date of Patent: October 6, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Reecha Jajodia, Gaurav Goyal
  • Virtualized interrupt delay mechanism
    Patent number: 9152587
    Abstract: A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned interrupt controller (14) can determine if the delay command can be performed based on local access control information.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: October 6, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bryan D. Marietta, Gary L. Whisenhunt, Kumar K. Gala, David B. Kramer
  • System for reducing dynamic power consumption of wakeup source
    Patent number: 9152207
    Abstract: A system for reducing dynamic power consumption of a wakeup source includes a receiver interface coupled to the wakeup source. A data packet, received by the receiver interface, transmits the data packet to the wakeup source. The wakeup source processes the data packet to identify a predetermined code for initiating a wakeup sequence. The wakeup source is put into a deep sleep mode if it is idle for a predetermined time period.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: October 6, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Gur Prasad Srivastava, Parampreet Singh Baweja, Rohit Gupta
  • Semiconductor device with selectively etched surface passivation
    Patent number: 9153448
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: October 6, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
  • Code coverage circuitry
    Patent number: 9153346
    Abstract: A method with a circuit that includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102), coupled to the memory and to the analog line coverage circuit, enables the analog line coverage circuit when the processor is in a debug mode.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: October 6, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rafael M. Vilela, Walter Luis Tercariol, Fernando Zampronho Neto, Sandro A. P. Haddad
  • Method for low power boot for microcontroller
    Patent number: 9152430
    Abstract: A microcontroller includes a clock generator having an internal reference clock, a system mode controller establishing an operating mode, a flash memory having an internal clock and a non-volatile option register, and a boot mode selection logic circuit coupled to the system mode controller and the flash memory. The logic circuit outputs a boot mode selection signal instructing the microcontroller to boot in a very low power run (VLPR) mode or a RUN mode. The system mode controller enters the VLPR or RUN mode in response. The flash memory bypasses and disables its internal clock prior to calibration of the flash memory in the VLPR mode and prior to initialization of the flash memory in the RUN mode. The flash memory subsequently uses an external clock signal based on the output of the internal reference clock.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: October 6, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Prashant Bhargava, Mohit Arora, Martin Mienkina, Sudhi R. Proch