Abstract: An apparatus and method for monitoring general purpose input output, GPIO, signals at GPIO pins of a GPIO port of a system on chip, SoC. The apparatus comprises a first checksum generation unit adapted to generate a first checksum on the basis of GPIO bits stored in GPIO registers of the SoC, being connected via corresponding input output, IO, pad circuits to provide analog GPIO signals at the GPIO pins. A second checksum generation unit is adapted to generate a second checksum on the basis of the analog GPIO signals at the GPIO pins representing the GPIO bits. Checker logic is adapted to compare the first checksum generated by the first checksum generation unit with a second checksum generated by the second checksum generation unit.

Abstract: A master device has a slave port and a redundant slave port for communicating with slaves according to a network protocol, e.g. EtherCAT, via data packets including a circulating bit. The slaves are arranged in a sequence starting at the slave port, and are connected via a communication medium. A respective slave in the sequence detects whether the connection to its processing receiver is lost, and, if so, internally transfers any data packets from its forwarding arrangement to its processing arrangement, while setting the circulating bit. The master device has a switcher unit coupled to the redundant slave port and a last slave in the sequence. The switcher unit transfers data packets from the switcher receiver to the switcher transmitter, and detects whether a circulating bit is set. If so, the unit switches off said transferring and switches on a connection between the redundant slave port and the switcher for transferring replicated packets to the sequence.

Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-43) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).

Abstract: A voltage level shifter module comprising at least one input arranged to receive an input signal, and at least one cascode transistor arranged to receive at a gate thereof at least one reference voltage signal. The voltage level shifter module further comprises at least one reference voltage control component arranged to detect logical state transitions within the input signal from at least a first logical state to a second logical state, and cause the reference voltage signal applied to the gate of the at least one cascode transistor to be pulled down to a reduced voltage upon detection of a logical state transition within the input signal from at least a first logical state to a second logical state.

Abstract: Embodiments of an electronic circuit comprise a module, such as a security module, configured to perform cryptographic processing for a predetermined security protocol that includes random number checking. The security module is controlled by a descriptor that includes instructions that cause the security module to access a generated random number, compare the generated random number to a random number stored during a previous execution of the descriptor, and generate an error signal when the generated random number and the previous execution random number are equal.

Abstract: A method for a packaged leadless semiconductor device including a heat sink flange to which semiconductor dies are coupled using a high temperature die attach process. The semiconductor device further includes a frame structure pre-formed with bent terminal pads. The frame structure is combined with the flange so that a lower surface of the flange and a lower section of each terminal pad are in coplanar alignment, and so that an upper section of each terminal pad overlies the flange. Interconnects interconnect the die with the upper section of the terminal pad. An encapsulant encases the frame structure, flange, die, and interconnects with the lower section of each terminal pad and the lower surface of the flange remaining exposed from the encapsulant.

Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).

Abstract: A device includes a semiconductor substrate, a drift region in the semiconductor substrate and having a first conductivity type, an isolation region within the drift region, and around which charge carriers drift on a path through the drift region during operation, and a protection region adjacent the isolation region in the semiconductor substrate, having a second conductivity type, and disposed along a surface of the semiconductor substrate.

Abstract: Systems and methods for providing compressed video with layered graphics to at least one screen are described herein. An On Screen Display (OSD) system receives a command from a remote set top box coupled to a screen. The command instructs the OSD system to process the input video stream according to various processing functions including layering at least one graphics plane on top of the video stream. The OSD system processes the input video stream to generate an output video stream with the layered graphics planes and outputs, in a compressed format, the output video stream to the screen. The system advantageously provides a central OSD processing unit that can output video with layered graphics in a compressed format to multiple displays.

Abstract: Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package.

Abstract: A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address.

Abstract: Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces.

Abstract: Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.

Abstract: A chip damage detection device is provided that includes at least one bi-stable circuit having a first conductive line passing through an observed area of a semiconductor integrated circuit chip for damage monitoring of the observed area. The at least one bi-stable circuit is arranged to flip from a first stable state into a second stable state when a potential difference between a first end and a second end of the first conductive line changes or when a leakage current overdrives a state keeping current at the first conductive line. Further, a semiconductor integrated circuit device that includes the chip damage detection device and a safety critical system that includes the semiconductor integrated circuit device or the chip damage detection circuit is provided.

Abstract: A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.

Abstract: A multi-mass resonator and a common-mode detection circuit are provided. The common-mode detection circuit, for example, may include a plurality of sensing electrodes, an interface circuit configured to interface with the plurality of sensing electrodes, and a common-mode capacitance extractor circuit electrically coupled in parallel to the interface circuit and configured to detect common-mode capacitance between the plurality of sensing electrodes and output a voltage representative the detected common-mode capacitance, and a differential-mode capacitance extractor circuit electrically coupled in parallel to the interface circuit and configured to detect differential-mode capacitance between the plurality of sensing electrodes and output a voltage representative the detected differential-mode capacitance.

Abstract: A processing system has a stored, encrypted data structure that is decrypted to provide verification data values. System data values are retrieved from locations distributed about a memory storing system data. The verification data values are compared with corresponding system data values to determine if a predetermined threshold of verification data values matches the system data values. The system resumes operation if the predetermined threshold is met.

Abstract: A method for providing memory protection within a signal processing system comprises receiving a memory access signal comprising at least one instruction memory region (IMR) indication. The IMR indication comprises an indication of a region of memory from which a memory access instruction was fetched, execution of said memory access instruction having resulted in the generation of the received memory access signal. The method further comprises comparing the IMR indication for the received memory access signal to at least one permitted memory region (PMR) indication for a target address of the received memory access signal, and determining whether a memory access being attempted by the memory access signal is permitted based at least partly on the comparison of the IMR indication for the received memory access signal to the PMR indication for the target address of the received memory access signal.

Abstract: Hardware processors in an SOC integrated circuit logically swapping memories by remapping memory addresses, including tightly coupled and local memories, to enable a sequence of data-processing algorithms to execute more quickly by different hardware processors without having to copy the data between different memories using a relatively slow data crossbar switch. When a memory stores error-correction code (ECC) address information linking stored ECC data with stored user data, the hardware processor dynamically remaps the ECC address information, as needed.

Abstract: An interrupt controller for controlling processing of interrupt requests by a plurality of processing units. The processing units have at least two modes: an active mode and an inactive mode. The interrupt controller comprises a controller input, an interrupt router coupled to the controller input and a monitoring unit. The monitoring unit outputs a routing change signal to the interrupt router if it determines that a selected processing unit, to which, in response to a received interrupt request, an execution of an interrupt service routine was initially routed, is in inactive mode while a preselected one is in the active mode. The interrupt router reroutes the execution of the interrupt service routine to the preselected processing unit.