Abstract: The present application suggests an electronic device and method for generating clock signals with and without frequency jitter for one source clock signal generated by a single narrow-band source clock signal. The device comprises a random number generator to generate a random number signal varying in time which represents a divisor fraction signal; a signal mixer to mix the timely varying random number signal and a clock divisor signal and to output a mixed divisor signal; and a fractional clock divider to generate an output clock signal from a source clock signal, wherein the output clock signal has a frequency fout(t), which is substantially equal to the frequency fsource of the source clock signal being a narrow-band clock signal divided by a divisor D(t) represented by the mixed divisor signal.

Abstract: An integrated circuit, such as for example an application specific integrated circuit, as well as a method of testing such a circuit, are disclosed herein. In one example embodiment, the integrated circuit includes a plurality of pins including a power pin, a ground pin, and a first communication pin, a test mode circuit, and a communication circuit. The integrated circuit additionally includes a first switch connected to the first communication pin, where the first switch is configured to couple the first communication pin to either the test mode circuit or the communication circuit. The integrated circuit further includes a control circuit coupled to the first switch and configured to control whether the first switch is operated to couple the first communication pin to the test mode circuit or to the communication circuit based upon or in response to an operating mode.

Abstract: The embodiments described herein provide compensation for mutual inductance in a multi-path device. In one embodiment, a device includes a multi-path integrated device. The multi-path integrated device includes a first output and a second output. The first output is configured to be coupled to a first output lead through a first bonding wire, and the second output is configured to be coupled to a second output lead through a second bonding wire. Due to their proximity, the second bonding wire has a first mutual inductance with the first bonding wire. A first compensation network is coupled to the first output, and a second compensation network is coupled to the second output. The second compensation network is configured to have a second mutual inductance with the first compensation network. The second mutual inductance at least partially cancels the effects of the first mutual inductance.

Abstract: A level shifter includes a first branch and a second branch. A trigger of the first branch is coupled to a low voltage input, an inverted high voltage output and a ground. A latch of the first branch is coupled to the inverted high voltage output and a high voltage output. A power gate of the first branch is coupled to an inverted low voltage input, the latch of the first branch and a high voltage supply. A trigger of the second branch is coupled to the inverted low voltage input, the high voltage output and the ground. A latch of the second branch is coupled to the high voltage output and the inverted high voltage output. A power gate of the second branch is coupled to the low voltage input, the latch of the second branch and the high voltage supply.

Abstract: A method for identifying a current context during execution of application program code. The method comprises the steps of retrieving static context information for the application program code, identifying at least one active section of the application program code loaded in physical memory; and identifying a current context based at least partly on the at least one identified active section and retrieved static context information.

Abstract: Forming a memory structure includes forming a charge storage layer over a substrate; forming a first control gate layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the control gate electrodes; and forming select gate electrodes adjacent the control gate electrodes.

Abstract: A method and apparatus for testing operation of a random number generator (RNG) testing circuit are provided. In accordance with at least one embodiment, a first RNG output value obtained from a RNG is stored in a first register. In response to activation of a test mode to simulate a faulty RNG, the first RNG output value is stored in a second register. The first RNG output value in the first register is compared to the first RNG output value in the second register. In response to the comparing, a RNG failure signal is provided at a RNG testing circuit output of the RNG testing circuit. In accordance with at least one embodiment, sequential and combinational logic can simulate a faulty RNG. Accordingly, simulation of a faulty RNG may be performed to test a RNG testing circuit even when the RNG is not faulty.

Abstract: A semiconductor device package is assembled using a jig that alters the shape of gel material disposed in a cavity in the package. In one embodiment, a jig having a concave bottom surface is inserted onto uncured gel material disposed within a cavity in a housing of the package to change a top surface of the gel from having a concave shape to a convex shape. The gel is then cured with the jig in place. When the jig is subsequently removed, the cured gel retains the convex shape, which helps to avoid any bond wires from being exposed. The re-shaped gel material reduces internal stresses during thermal cycling and can therefore reduce permanent damage to the package otherwise resulting from such thermal cycling.

Abstract: A device and a method for performing bitwise manipulation is provided. Multiple bitwise logic circuits are coupled to an instruction decoder, a register array and a rotator. Each bitwise logic circuit includes input multiplexers connected to an output multiplexer. The instruction decoder receives a bit manipulation instruction and sends to each corresponding input multiplexer a control signal based on a type of the instruction. Each input multiplexer of each bitwise logic circuit receives a control signal, a constant signal that has a value that is indifferent to the value of the mask, and a mask affected signal that has a value that is responsive to a value of an associated mask bit. Each input multiplexer selects between the constant signal and the mask affected signal based on the control signal, and outputs a selected signal.

Abstract: A receiver and a method for providing block synchronization of symbols and integral frequency offset correction of subcarriers are provided. Samples of a received signal are transformed into the frequency domain. Subcarrier extraction is performed to extract selected subcarriers. The extracted subcarriers are differentially demodulated using subcarriers from the previous symbol and coherently combined with reference subcarrier values to obtain sample vectors. The sample vectors are obtained over a number of symbols preferably equal to the number symbols in a block. Cyclic correlation is performed on those sample vectors relative to a known synchronization (sync) pattern. A maximum magnitude search is performed over sample vectors obtained from the cyclic correlation to determine an integral frequency offset and a block boundary of the received signal. The integral frequency offset and the block boundary can be used to tune and synchronize the receiver for proper reception of the received signal.

Abstract: An integrated circuit device comprising at least one prefetching module for prefetching lines of data from at least one memory element. The prefetching module is configured to determine a position of a requested block of data within a respective line of data of the at least one memory element, determine a number of subsequent lines of data to prefetch, based at least partly on the determined position of the requested block of data within the respective line of data of the at least one memory element, and cause the prefetching of n successive lines of data from the at least one memory element.

Abstract: A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.

Abstract: A data processing system comprises a processor unit that includes an instruction decode/issue unit including a re-order buffer having entries that include an execution queue tag that indicates an execution queue location of an instruction to which a re-order buffer entry is assigned, a result valid indicator to indicate that a corresponding instruction has executed with a status bit valid result, and a forward indicator to indicate that the status bit can be forwarded to an execution queue of an instruction pointed to that is waiting to receive the status bit.

Abstract: A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region. An NVM structure is formed in the NVM region. The NVM structure includes a control gate structure and a select gate structure. A protective layer is formed over the NVM structure. A gate dielectric layer is formed over the substrate in the logic region. The gate dielectric layer includes a high-k dielectric. A sacrificial gate is formed over the gate dielectric layer in the logic region. A first dielectric layer is formed around the sacrificial gate. Chemical mechanical polishing is performed on the NVM region and the logic region after forming the first dielectric layer. The sacrificial gate is replaced with a metal gate structure.

Abstract: A mechanism for improving speed of table model-based simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having substantially the same properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, a cache lookup is performed to determine table model solution values for the previously-evaluated transistor or device, and those values are used to determine exact output values per the table model of the presently being evaluated transistor or device.

Abstract: An integrated circuit facilitates a self test routine that verifies proper operation of an analog comparator. In response to entering the self test routine, the voltage provided to an input of a comparator is changed from being at an operating voltage supply to being at a self test voltage that is used to verify operation of the comparator. In response to the comparator operating properly, the self test voltage provided to the input of the comparator is replaced with the operating voltage supply, and normal operation resumes. The duration of the self test cycle is based upon the amount of time during which the self test voltage is provided to the comparator is asynchronous in nature, and therefore not a function of a clock signal.

Abstract: A stacked die sensor package includes a die paddle and lead fingers that surround the die paddle. The lead fingers have proximal ends near the die paddle and distal ends spaced from the die paddle. A first semiconductor die is mounted to one side of the die paddle and electrically connected to the lead fingers with first bond wires. A sensor die is mounted to the other side of the die paddle and electrically connected to the lead fingers with sensor bond wires. An encapsulation material covers the first die and the first bond wires, while a gel material and a lid cover the sensor die and the sensor bond wires. The package may also have a second semiconductor die attached on an active surface of the first die and electrically connected one or both of the lead fingers or first die bonding pads with second bond wires.

Abstract: A device includes a Doherty amplifier. The Doherty amplifier has a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a resistive switch having a first terminal connected to the peaking path and a second terminal connected to a voltage reference, and a controller configured to set the resistive switch to a first resistance value when a power input of the Doherty amplifier is below a threshold and to a second resistance value when the power input of the Doherty amplifier is above the threshold.

Abstract: A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.

Abstract: Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of manufacturing a semiconductor device that includes the disclosed deep trench isolation structures. The methods also include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.