Abstract: A method and apparatus for deriving a packet select probability value for a data packet. The method comprises determining a queue length value for a target buffer of the data packet, calculating a queue congestion value based at least partly on the queue length value and a packet select queue length range, and calculating the packet select probability value for the data packet based at least partly on an exponential function e?x, where x is computed based at least partly on the queue congestion value.

Abstract: A method and apparatus are provided for error correction of a memory by using a first memory (18), second memory (14), and redundant memory (19) to perform error correction code (ECC) processing on data retrieved from the first memory (18) by using the redundant memory (19) to replace entries in the second memory (14) having repeat addresses, thereby freeing entries in the second memory (14) for use in detecting and managing errors identified by the ECC processing.

Abstract: A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit. Each of the data sources is capable of providing a data stream. The memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer. Each of the buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer. The memory control unit is arranged to allocate and de-allocate memory regions to and from each of the buffers in dependence of the buffer characteristics of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers. A method of operating a system on chip is also described.

Abstract: An electronic apparatus includes a packaging enclosure, first and second die pads disposed within the packaging enclosure, first and second semiconductor die disposed on the first and second die pads, respectively, a plurality of packaging leads, each packaging lead projecting outward from the packaging enclosure, a plurality of packaging posts disposed within the packaging enclosure and extending inward from opposite sides of the packaging enclosure between the first and second die pads, each packaging post being connected with a respective one of the plurality of packaging leads, and a plurality of wire bonds disposed within the packaging enclosure. Each packaging post of the plurality of packaging posts is connected via a first wire bond of the plurality of wire bonds to the first semiconductor die and via a second wire bond of the plurality of wire bonds to the second semiconductor die.

Abstract: An integrated circuit includes a signal line for carrying a radio frequency signal; a coupling line inductively coupled to the signal line for delivering an induced signal in dependence on the radio frequency signal; a connecting line connected to a pick-off point of the coupling line for picking off the induced signal from the coupling line; and a conductive part for shielding the coupling line against electromagnetic interference and for enhancing inductive coupling between the signal line and the coupling line. The conductive part may have a uniform flat surface facing the coupling line. The signal line may extend parallel to the surface. The coupling line may extend parallel to the signal line and may be arranged between the surface and the signal line.

Abstract: A quantizer for an analog to digital converter has an input for receiving an analog input signal. A detector senses a common mode voltage component of the input signal. A reference voltage source produces a plurality of reference voltages. A voltage source biases the reference voltage source in response to the sensed common mode voltage component. Therefore, the common mode voltage in the input signal establishes the common mode voltage of the reference voltage source. A plurality of comparators are connected to the reference voltage source, wherein each of the plurality of comparators compares the input signal to one of the plurality of reference voltages and produces a output bit denoting a result of the comparing.

Abstract: An audio unit, connected or connectable to a safety-critical apparatus, or integrated or integrable in the apparatus, is proposed. The audio unit may comprise a driver unit, a detection unit, and an alert unit. The driver unit may generate an analog audio signal in response to a request from the apparatus, to drive an acoustic output unit and thereby generate an acoustic signal for a user of the apparatus. The detection unit may detect the audio signal. The alert unit may generate an alert signal in response to the request if the detection unit has not detected the audio signal. It can thus be checked whether the acoustic signal is generated. A method for generating a safety critical acoustic signal is also described.

Abstract: A There is proposed a method and device for simulating a semiconductor IC is provided, which comprises generating a high level description of the IC, generating a low level description of the IC comprising a plurality of instances describing the operation of the IC, conducting a low level function analysis of the IC based on metrics values associated with the instances, and performing a design optimization scheme. The scheme comprises mapping the metric values of instances describing functional units different from standard cells, to standard cells logically connected to said instances, by dividing each of the instance metrics values between a group of standard cells logically connected to the corresponding instance and adding each resulting portion of said instance metric value to the metric value of each of the group of standard cells, respectively.

Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.

Abstract: A thermal sensor system which includes a thermal sensor and a voltage control network which applies a reference voltage level and a delta voltage level to the same or different thermal sensors. The thermal sensor develops a reference current signal in response to the reference voltage level and a delta current signal in response to the delta voltage level. A current gain network adjusts gain of the delta current signal. A current compare sensor, which is responsive to the reference current signal and the delta current signal, provides a comparison metric. A controller controls the current gain network to adjust gain of the delta current signal while monitoring the comparison metric to determine a gain differential value indicative of a current ratio between the current signals. The controller determines a temperature value based on the gain differential value. A LUT may be used to retrieve the temperature.

Abstract: A system and method are disclosed for determining whether to allow or deny an access request based upon one or more descriptors at a local memory protection unit and based upon one or more descriptors a system memory protection unit. When multiple descriptors of a memory protection unit apply to a particular request, the least-restrictive descriptor will be selected. System access information is stored at a cache of a local core in response to a cache line being filled. The cached system access information is merged with local access information, wherein the most-restrictive access is selected.

Abstract: A device includes an amplifier having a first path and a second path and a first variable attenuator connected to the first path. The device includes a controller coupled to the first variable attenuator. The controller is configured to determine a magnitude of an input signal to the amplifier. When the magnitude of the input signal is below a threshold, the controller is configured to set an attenuation of the first variable attenuator to a first attenuation value. When the magnitude of the input signal is above the threshold, the controller is configured to set the attenuation of the first variable attenuator to a second attenuation value. The second attenuation value is less than the first attenuation value.

Abstract: A resistive random access memory (ReRAM) cell, comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and an interface region comprising a plurality of interspersed field focusing features that are not photo-lithographically defined. The interface region is located between the first conductive electrode and the dielectric storage material layer or between the dielectric storage material layer and the second conductive electrode.

Abstract: An integrated circuit device comprising at least one electrostatic discharge (ESD) clamp device. The at least one ESD clamp device comprises a first channel input, a second channel input, and a control input arranged to receive a control signal. The at least one ESD clamp device is arranged to selectively operate in a conductive state in which the at least one ESD clamp device permits current to flow between the first and second channel inputs thereof based at least partly on the received control signal. The integrated circuit device further comprises at least one biasing module. The at least one biasing module comprises at least one output operably coupled to the control input of the at least one ESD clamp device, and at least one input arranged to receive a thermal regulation signal. The at least one biasing module being arranged to apply a bias to the control signal for the at least one ESD clamp device based at least partly on the received thermal regulation signal.

Abstract: A pipeline circuit determines a first effective address based a sum of a first value and a second value. The first effective address is based upon an actual value of a carry-in into a bit-wise region of the first and second values. The bit-wise region includes a predefined internal region of bits of the first and second values. The pipeline circuit also determines a second effective address based a sum of a third value and a fourth value. A collision detector circuit receives bits from the bit-wise region of each of the four values and determines a plurality of speculative results based upon the bits of the bit-wise regions and based upon a plurality of speculative carry-in values. A collision indicator is asserted based on at least one result of the plurality of speculative results, and the actual values of the first and second carry-in.

Abstract: A microelectromechanical system (MEMS) package is disclosed herein. The MEMS package includes a movable mass. The MEMS package further includes a first and second sense electrodes spaced apart from the movable mass. The first and second sense electrodes are configured to be electrically coupled with a controller. The MEMS package further includes a first test electrode and a second test electrode spaced apart from the movable mass. The first and the second test electrodes are configured to be electrically connected to first and second external electrical connectors, respectively. The first and second test electrodes are biased at a first voltage and a second voltage, respectively, when the first and second external electrical connectors are connected to external voltage sources.

Abstract: A digital sample clock generator for generating a sample clock signal from an input signal derived from a drive measurement voltage signal of a vibrating MEMS gyroscope is provided.

Abstract: An integrated circuit device comprising at least one analog to digital converter. The at least one ADC comprises at least one input operably coupled to at least one external contact of the integrated circuit device. The integrated circuit device further comprises detection circuitry comprising at least one detection module. The at least one detection module being arranged to receive at a first input thereof an indication of a voltage level at the at least one input of the at least one ADC, compare the received indication to a threshold value, and if the received indication exceeds the threshold value, output an indication that an excessive voltage state at the at least one input of the at least one ADC has been detected.

Abstract: An integrated circuit device comprising at least one radio frequency (RF) transceiver module. The at least one RF transceiver module includes a plurality of low noise amplifiers (LNAs) operably coupled to external contacts of the integrated circuit device and arranged to receive an RF signal from the respective external contact, amplify the received RF signal, and to output the amplified RF signal. Each transceiver module further includes a plurality of power amplifier (PA) modules operably coupled to the external contact of the integrated circuit device, and arranged to receive an RF signal to be transmitted, amplify the received RF signal to be transmitted, and output the amplified signal. The plurality of LNAs and the plurality of PAs are selectively configurable to operate in at least a first, multi-antenna configuration and a second, single antenna high transmit power configuration.

Abstract: A channel estimation processor for a receiver in a wireless communication system is described. The channel estimation processor includes a stage-1 processor (STG1) arranged to pluralities of Nsym reference symbol correlation values per slot. The channel estimation processor includes a stage-2 processor (STG2) comprising a plurality of stage-2a processors for obtaining filtered outputs per slot, a respective plurality of stage-2b processors for obtaining respective slot filter results and a stage-2 adder (STG2ADD) for obtaining channel estimates for respective anchor positions. The stage-2a processors are arranged to filter respective pluralities of reference symbol correlation values using respective reference symbol filters (ga) to obtain a respective filtered output per slot.